Full-bridge tip driver for active stylus
Granted: August 11, 2015
Patent Number:
9104251
A method and apparatus to increase a transmit (TX) signal generated by an active stylus without increasing the power consumption of the active stylus. In one aspect, the active stylus increases the amplitude of the TX signal. In another aspect, the active stylus increases the TX signal by providing the capacitance of a body of a user to the stylus.
Optical navigation module with capacitive sensor
Granted: August 11, 2015
Patent Number:
9103658
Optical navigation modules and methods of operating the same to sense relative movement between the optical navigation module and a tracking surface are provided. In one embodiment, the optical navigation module comprises: (i) a light source to illuminate at least a portion of a surface relative to which the optical navigation module is moved; (ii) an integrated circuit (IC) including a photo-detector array (PDA) to detect a light pattern propagated onto the PDA from the surface, and a…
Method of ONO integration into logic CMOS flow
Granted: August 11, 2015
Patent Number:
9102522
An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel…
Configurable bus
Granted: August 4, 2015
Patent Number:
9098641
A configurable bus includes a plurality of bus segments. The configurable bus also includes two or more pluralities of input/output (I/O) ports. Each bus segment is coupled to at least one of the pluralities of I/O ports. Also coupled to the bus segments is a cross-couple unit that is configurable to selectively couple any of the bus segments together.
Device and method of establishing sleep mode architecture for NVSRAMs
Granted: August 4, 2015
Patent Number:
9098270
A device is configured to establish first and second device power domains. Isolation circuits isolate signals from passing between circuits in the first device power domain and circuits in the second device power domain. During a transition between power domains, an n-bit value is stored in a particular storage location, and compared to a particular n-bit value. Isolation between the first and second device power domains is removed when the n-bit value stored in the particular storage…
Adaptive ambient light auto-movement blocking in optical navigation modules
Granted: August 4, 2015
Patent Number:
9098144
Embodiments of optical navigation modules (ONM) and methods of operating the same to block auto-movement due to ambient light are described. Generally, the method includes: (i) collecting a plurality of PD signal samples from a photodiode (PD) in an optical navigation module (ONM); (ii) determining a peak-to-peak variation (?PD) in the plurality of PD signal samples; (iii) comparing the peak-to-peak variation (?PD) to a specified threshold peak-to-peak variation (?PDSPEC); and (iv) if…
Memory transistor with multiple charge storing layers and a high work function gate electrode
Granted: July 28, 2015
Patent Number:
9093318
A memory device is described. Generally, the device includes a memory transistor and a metal oxide semiconductor (MOS) logic transistor. The memory transistor includes: a channel region electrically connecting a source region and a drain region, the channel region comprising polysilicon; an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, the ONNO stack comprising a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an…
Low power, low pin count interface for an RFID transponder
Granted: July 28, 2015
Patent Number:
9092582
A serial interface includes a select node, a clock node, a first bidirectional data port, a second bidirectional data port, and shift register circuitry coupled to both data ports such that a leading edge and a falling edge of a clock signal associated with the clock node are used to shift or transfer data.
Method and apparatus to improve noise immunity of a touch sense array
Granted: July 28, 2015
Patent Number:
9092098
A method for improving noise immunity of capacitive sensing circuit associated with a touch sense array is disclosed. The capacitive sensing circuit receives a response signal from a touch sense array. The capacitive sensing circuit measures a noise component of the response signal. When a level of noise of the noise component within a passband of the capacitive sensing circuit is greater than a threshold, the capacitive sensing circuit changes at least one parameter of capacitive…
Dynamic mode switching for fast touch response
Granted: June 30, 2015
Patent Number:
9069405
A method of operating a touch-sensing surface may include determining a presence of at least one conductive object at the touch-sensing surface by performing a search measurement of a first set of sensor elements of the touch-sensing surface, and in response to determining the presence of the at least one conductive object, determining a location of the at least one conductive object by performing a tracking measurement of a second set of sensor elements of the touch-sensing surface.
Power savings apparatus and method for memory device using delay locked loop
Granted: June 2, 2015
Patent Number:
9047237
Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is…
Hard press rejection
Granted: May 26, 2015
Patent Number:
9043183
Techniques for hard press rejection are described herein. In an example embodiment, a touch area on a sensor array is determined, where the touch area corresponds to a detected object and is associated with multiple signal values. A slope value for the detected object is computed based on a ratio of a signal distribution value in the touch area to a metric indicating a size of the touch area with respect to the sensor array. The slope value is compared to a threshold in order to…
Programmable and flexible reference cell selection method for memory devices
Granted: May 26, 2015
Patent Number:
9042150
An exemplary system includes an array of interconnected cells and a flexible decoder. The array is configured to receive a selection signal as input, select a cell based upon the selection signal, and provide an output based on the selected cell. The flexible decoder is configured to receive an input, generate a selection signal based on the input and one or more characteristics of the array of interconnected cells, and provide the selection signal to the array of interconnected cells.
System and method for multi-layer global bitlines
Granted: May 26, 2015
Patent Number:
9041203
A system and method for manufacturing a semiconductor device including multi-layer bitlines. The location of the bitlines in multiple layers provides for increased spacing and increased width thereby overcoming the limitations of the pitch dictated by the semiconductor fabrication process used. The bitlines locations in multiple layers thus allows the customization of the spacing and width according to the use of a semiconductor device.
Method and apparatus for staggered start-up of a predefined, random or dynamic number of flash memory devices
Granted: May 19, 2015
Patent Number:
9036423
A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for…
DC-DC converter, control circuit, and power supply control method
Granted: May 19, 2015
Patent Number:
9035632
A DC-DC converter includes a first amplifier that amplifies a first difference between a first reference voltage and a feedback voltage corresponding to an output voltage, a second amplifier that amplifies a second difference between the first reference voltage and an integrated value of the feedback voltage, and a controller that controls a switching circuit to change the output voltage when the first difference reaches the second different.
Simultaneously forming a dielectric layer in MOS and ONO device regions
Granted: May 5, 2015
Patent Number:
9023707
Methods of ONO integration into MOS flow are provided. In one embodiment, the method comprises: (i) forming a pad dielectric layer above a MOS device region of a substrate; and (ii) forming a patterned dielectric stack above a non-volatile device region of the substrate, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer, the charge-trapping layer comprising multiple layers including a first nitride layer formed on the tunnel…
Deuterated film encapsulation of nonvolatile charge trap memory device
Granted: April 28, 2015
Patent Number:
9018693
Nonvolatile charge trap memory devices with deuterium passivation of charge traps and methods of forming the same are described. In one embodiment, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device. A gate stack overlies the channel, the gate stack comprising a tunneling layer, a trapping layer, a blocking layer, a gate layer; and a deuterated gate cap layer. The gate cap layer has a…
Low pin count solution using capacitance sensing matrix for keyboard architecture
Granted: April 28, 2015
Patent Number:
9019133
An apparatus and method for selecting a keyboard key based on a position of a presence of a conductive object on a sensing device and a pre-defined area of the keyboard key. The apparatus may include a sensing device and a processing device. The sensing device may include a plurality of sensor elements to detect a presence of a conductive object on the sensing device. Multiple keyboard keys are assigned to pre-defined areas of the sensing device. The processing device is coupled to the…
Universal digital block interconnection and channel routing
Granted: April 28, 2015
Patent Number:
9018979
A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional…
