DIGITAL PULSE FREQUENCY/PULSE AMPLITUDE (DPFM/DPAM) CONTROLLER FOR LOW-POWER SWITCHING-POWER SUPPLIES
Granted: September 18, 2008
Application Number:
20080225938
A digital controller for dc-dc switching converters can operate under light load conditions. The controller can be suitable for the use in switch-mode power supplies providing regulated output voltage for handheld devices and other low-power electronics. To create long time intervals, compared to the propagation time of digital logic a DPFM/DPAM can use a ring oscillator with two sets of delay cells and two signals racing around the ring.
DIGITAL PULSE-WIDTH MODULATOR BASED ON NON-SYMMETRIC SELF-OSCILLATING CIRCUIT
Granted: September 18, 2008
Application Number:
20080224756
A low-power digital pulse-width modulator (DPWM) architecture for high frequency dc-dc switch-mode power supplies (SMPS) is disclosed that is well-suited for integration in power management systems of small handheld devices. The DPWM can operate in a stand-alone mode, without external clock, and can be implemented on a portion of silicon area needed for other DPWM solutions. In addition it has low power consumption and provides a good linearity of the input-to-output characteristic, also…
MEANS TO CONTROL PLL PHASE SLEW RATE
Granted: September 11, 2008
Application Number:
20080218276
A charge pump includes a multitude of current sources and current sinks adapted to supply current to or discharge current from a loop filter. The paths between current sources/sinks and the loop filter are selectively activated or deactivated to enable current to flow from the current source(s) to the loop filter or flow from the loop filter to the current sinks(s). Accordingly, the charge pump is adapted to provide more than one bandwidth depending on the bit levels of a select signal.…
MEANS TO CONTROL PLL PHASE SLEW RATE
Granted: September 11, 2008
Application Number:
20080218278
A charge pump includes a multitude of current sources and current sinks adapted to supply current to or discharge current from a loop filter. The paths between current sources/sinks and the loop filter are selectively activated or deactivated to enable current to flow from the current source(s) to the loop filter or flow from the loop filter to the current sinks(s). Accordingly, the charge pump is adapted to provide more than one bandwidth depending on the bit levels of a select signal.…
Wide-input windowed nonlinear analog-to-digital converter for high-frequency digitally controlled SMPS
Granted: August 28, 2008
Application Number:
20080204296
In embodiments, a new analog-to-digital converter (ADC) architecture can be used with switch-mode power supplies (SMPS) operating at switching frequencies higher than 10 MHz. Analog-to-digital converter embodiments can achieve very low power consumption, fast conversion time, and can be implemented with a simple hardware. Another noteworthy benefit is that certain ADC embodiments feature a non-linear gain characteristic that provides improved load transient response for digital…
Variable sub-bandgap reference voltage generator
Granted: November 8, 2007
Application Number:
20070257655
A sub-bandgap reference voltage generator, generates a pair of variable voltages one having a positive temperature coefficient and one having a negative voltage coefficient. The pair of voltages are added to generate an output voltage whose value and temperature may be varied. To achieve this, a first voltage having a positive temperature coefficient is multiplied by a first ratio defined by first and second resistive values to generate a second voltage. A third voltage having a negative…
TAPER TOOL ASSEMBLY
Granted: September 20, 2007
Application Number:
20070215289
In one embodiment, a taper tool assembly includes a body, a control sleeve, and at least one bearing surface. The body is configured to hold dry wall compound. The control sleeve is configured to move along at least a portion of a length of the body. The at least one bearing surface is positioned between the body and the control sleeve, the at least one bearing surface reducing friction between the body and the control sleeve.
Low Power Charge Pump
Granted: August 16, 2007
Application Number:
20070189429
A charge pump is configured to control current flow at an output node in response to input signals. A plurality of control signals are generated based upon the input signals. The control signals operate to control the timing and duration of current flows within the charge pump and to thereby reduce charge pump power consumption. Based upon the control signals, the conductivity of a first path between a power supply and the output node and a second path between the output node and a…
Phase detector for RZ
Granted: February 15, 2007
Application Number:
20070035333
A phase detector is adapted to receive first and second signals and generate third and fourth signals representative of the difference between the phases of the first and second signals. The phase detector assert the third signal in response to the assertion of the first signal and unasserts the third signal in response to the assertion of the second signal. The phase detector asserts the fourth signal in response to the assertion of the third signal and unasserts the fourth signal in…
Detection Of A Closed Loop Voltage
Granted: October 26, 2006
Application Number:
20060238263
To detect whether a closed-loop's voltage is out of range, a voltage detector includes first and second transistors that deliver first and second currents respectively to first and second high impedance nodes. The voltage detector further includes third and fourth transistors that draw third and fourth currents respectively from the first and second nodes. The first and second currents are scaled replicas of a current flowing through a current source of a voltage-to-current converter…
HIGH SPEED DIFFERENTIAL RESISTIVE VOLTAGE DIGITAL-TO-ANALOG CONVERTER
Granted: June 22, 2006
Application Number:
20060132343
A differential digital-to-analog voltage converter (VDAC) includes, in part, a resistor, and at least two decoding stages. The resistor is divided into N equal segments each disposed in a different one of N decoders forming a first decoding stage. The resistor segment in each decoder is further divided into M equal segments to provide M tapped nodes. Each decoder of the first decoding stage delivers two of the M tapped voltages to a pair of associated output nodes, and that are…
Differential operational amplifier
Granted: June 8, 2006
Application Number:
20060119431
The input stage of an operational amplifier includes at least four signal-receiving stages adapted to receive four primary input signals. If the voltage level associated with any of the input signal changes, at least one transistor in each of the at least four signal-receiving stages conducts more current and at least one transistor in each of these stages conducts less current. The four signal-receiving stages collectively generate at least four intermediate signals that are delivered…
Method and apparatus to generate break before make signals for high speed TTL driver
Granted: June 1, 2006
Application Number:
20060114028
A driver includes, in part, a delay chain having disposed therein a multitude of accessible nodes, and a control logic coupled to the various nodes of the delay chain to generate the signals applied to the gate terminals of the PMOS and NMOS transistors disposed in the driver. The nodes that are accessed and tapped may or may not be the successive nodes disposed along the delay chain. Optionally four nodes of the delay chain are tapped to supply signals to the control logic. Two of the…
REVERSE-BIASED P/N WELLS ISOLATING A CMOS INDUCTOR FROM THE SUBSTRATE
Granted: March 30, 2006
Application Number:
20060065947
A double well structure beneath an inductor to isolate it from the substrate. Contacts are provided for the deeper well and the substrate, to reverse bias the junction between the substrate and the deep well. In one embodiment, for a P-substrate, the deep well is an N-well, and the other well is a P-well. Both the N-well junction with the substrate, and the junction between the N-well and the P-well are reverse biased. This improves the quality factor of the inductor structure above the…
Detection of a closed loop voltage
Granted: March 30, 2006
Application Number:
20060066359
To detect whether a closed-loop's voltage is out of range, a voltage detector includes first and second transistors that deliver first and second currents respectively to first and second high impedance nodes. The voltage detector further includes third and fourth transistors that draw third and fourth currents respectively from the first and second nodes. The first and second currents are scaled replicas of a current flowing through a current source of a voltage-to-current converter…
Differential amplifier
Granted: February 16, 2006
Application Number:
20060033570
The input stage of an operational amplifier includes at least four signal-receiving stages adapted to receive four input signals. If the voltage level associated with any of the input signal changes, at least one transistor in each of the at least four signal-receiving stages conducts more current and at least one transistor in each of these stages conducts less current. The four signal-receiving stages collectively generate four intermediate signals that are delivered to the output…
Phase detector
Granted: January 26, 2006
Application Number:
20060017471
A phase detector is adapted to receive first and second signals and generate third and fourth signals representative of the difference between the phases of the first and second signals. The phase detector assert the third signal in response to the assertion of the first signal and unasserts the third signal in response to the assertion of the second signal. The phase detector asserts the fourth signal in response to the assertion of the third signal and unasserts the fourth signal in…
CMOS LvPECL driver with output level control
Granted: December 29, 2005
Application Number:
20050285637
A differential output driver includes an output block, a replication block, and a feedback control block. Each of the output and replication blocks further includes a preamplifier and a source-follower stage. The preamplifier of the output block receives a differential input voltage and generates a first differential voltage. The source-follower stage of the output block receives the first differential voltage and generates a differential output voltage. The preamplifier of the…
FREQUENCY COMPENSATION OF WIDE-BAND RESISTIVE GAIN AMPLIFIER
Granted: April 7, 2005
Application Number:
20050073364
A technique for minimizing the effect of parasitic capacitance in a resistive gain amplifier. Instead of the resistors being formed directly over the substrate, or over an oxide of the substrate, a semiconductor element (e.g., an n-well) is used between the resistor and the substrate. For resistors in the input circuit, this semiconductor element is connected to the voltage input rather than ground. For the resistors in the feedback loop circuit, the semiconductor element is connected to…
CMOS bandgap reference with low voltage operation
Granted: August 12, 2004
Application Number:
20040155700
A bandgap reference voltage generator includes, in part, a first closed-loop circuit having a first operational amplifier and adapted to generate a first current with a positive temperature coefficient and a second closed-loop circuit having a second operational amplifier and adapted to generate a second current with a negative temperature coefficient. The bandgap reference voltage generator is further adapted to include a multitude of output stages. Each output stage may be…
