CMOS analog switch with auto over-voltage turn-off
Granted: July 22, 2004
Application Number:
20040141273
An analog transfer gate that can be connected to an external line of a chip that is also connected to a digital circuit. The transfer gate includes both NMOS and PMOS transistors for passing the analog signals in both directions. A voltage sensing circuit is connected to the external line and is configured to sense a voltage that is higher than the supply voltage of the analog circuit. When this occurs, it produces a sense output signal. The sense output signal activates a protection…
Delay line and transistor with RC delay gate
Granted: May 6, 2004
Application Number:
20040085700
A method and apparatus for implementing trimming circuits. More particularly, embodiments of the present invention provide a transistor that supplies sufficient current to trim a trimming fuse when the transistor is powered up and after it receives a select signal at its gate. When the trimming fuse is trimmed, it decouples undesired electrical connections in a circuit. Also provided is a delay structure that adds an RC delay to the select signal. The RC delay is of a sufficiently long…
LOOP FILTER CAPACITOR MULTIPLICATION IN A CHARGE PUMP CIRCUIT
Granted: April 29, 2004
Application Number:
20040080359
A charge pump circuit with a small loop filter capacitor is disclosed in the invention. This is accomplished by providing multiple currents which add to the desired current, I. A switching circuit switches one of the currents through the capacitor, while directing a combination of the multiple currents through the resistors. In this way, a smaller current is provided through the capacitor, allowing the capacitor to be much smaller in size.
Pixel-by-pixel digital control of gain and offset correction for video imaging
Granted: April 22, 2004
Application Number:
20040075748
A method and apparatus for adjusting, on a pixel-by-pixel basis, the gain and offset in an AFE as the pixels are sequentially processed. Although the method can be used for any purpose, it is directed in particular to light source non-linearity, such as edge effects of a scanner. A unique clocking method clocks the gain and offset values into the register at a higher clock rate than the image sampling rate.
I/O PAD OVERVOLTAGE PROTECTION CIRCUITRY
Granted: March 11, 2004
Application Number:
20040046598
A protection circuit for a transmission gate having a PMOS transmission gate transistor and an NMOS transmission gate transistor coupled between a core circuit and an I/O pad. Biasing transistors are coupled to gates of the NMOS and PMOS transmission gate transistors to turn them on during normal operation. A protection circuit will turn off the NMOS and PMOS transmission gate transistors when the voltage at the pad exceeds the supply voltage by more than a threshold amount. This…
Interleaved pulse-extended phase detector
Granted: January 22, 2004
Application Number:
20040012414
A mechanism for dealing with faster clock speeds by increasing the pulse width of the pump-up and pump-down pulses of a Hogge-type phase detector without dividing the clock. In particular, the NRZ data stream is divided into two, interleaved data streams which are provided through two series of flip-flops. By connecting the exclusive-OR gates separately to the two series of flip-flops to generate the pump-up and pump-down pulses, a longer time between transitions can be achieved by…
SINGLE-SEED WIDE-SWING CURRENT MIRROR
Granted: November 6, 2003
Application Number:
20030205994
A current mirror circuit that uses only a single seed current, and thus only a single current source. A transistor biasing circuit is connected in between the single current source and the two transistors of the first leg of the current mirror. The transistor biasing circuit provides two functions. First, the source current itself flows through the transistors of the transistor biasing circuit to the two transistors forming the first leg of the current mirror. Second, the transistor…
BOUNCE TOLERANT FUSE TRIMMING CIRCUIT WITH CONTROLLED TIMING
Granted: October 23, 2003
Application Number:
20030197996
A method and apparatus for implementing trimming circuits. More particularly, embodiments of the present invention provide a transistor that supplies sufficient current to trim a trimming fuse when the transistor is powered up and after it receives a select signal at its gate. When the trimming fuse is trimmed, it decouples undesired electrical connections in a circuit. Also provided is a delay structure that adds an RC delay to the select signal. The RC delay is of a sufficiently long…
CMOS transmission gate with high impedance at power off
Granted: October 9, 2003
Application Number:
20030189455
A transmission gate circuit with high impedance during power off conditions, which includes a first transistor coupled between a first terminal and a second terminal and a second transistor coupled between the first terminal and the second terminal. Also included is a control circuit configured to monitor voltages on the first terminal and on a first voltage source, the control circuit configured to couple the gates of the first and second transistors to a voltage that will keep the…
Clock and data recovery circuit for return-to-zero data
Granted: October 9, 2003
Application Number:
20030190001
A converting circuit which converts RZ data into intermeidate NRZ data. The intermediate NRZ data is then sampled to detect a phase of the intermediate NRZ data, which corresponds to the phase of the RZ data. In a preferred embodiment, the converting circuit is incorporated in a modified Hogge NRZ phase detector. A toggle flip-flop is placed in front of the Hogge phase detector. Since the toggle flip-flop is triggered by the leading edge of the RZ pulse, it essentially converts the RZ…
Input termination with high impedance at power off
Granted: September 11, 2003
Application Number:
20030169068
An input termination circuit with high impedance at power off, which includes a first transistor coupled between a first terminal and a second terminal. The input termination circuit also includes a control circuit that monitors voltages on the first and second terminals and a first voltage source. During power off conditions, the control circuit couples the gate of the first transistor to a voltage that will keep the first transistor off. The first transistor remains off even when the…
POWER DOWN CIRCUIT FOR HIGH OUTPUT IMPEDENCE STATE OF I/O DRIVER
Granted: April 17, 2003
Application Number:
20030071660
A circuit for putting an output driver into a high impedance state upon failure of the power supply. This is accomplished by providing a first transistor that is connected between the power supply and the n-well to charge the n-well node of the PMOS drive transistor. Upon failure of the supply voltage, a number of transistors are connected to couple the n-well and a gate of the PMOS drive transistor to the output line, so that they track the voltage level of the output, thereby…
AUTOMATIC FREQUENCY RATE SWITCH
Granted: August 15, 2002
Application Number:
20020109533
A method and apparatus for automatically determining the protocol being used from the frequency of an applied clock without the need for a separate pin or switch or a second external clock. The clock's frequency is identified when its frequency falls into the set range for which the apparatus is targeted. Based on the detected frequency in the set range, a mode select signal is generated. The mode select signal causes the chip to configure to the appropriate frequency for that mode, as…
Digitally-controlled line build-out circuit
Granted: July 25, 2002
Application Number:
20020097808
A digital LBO in which digitized versions of the desired waveforms are stored in memory. A selection circuit allows the selection of certain ones of said waveforms corresponding to an anticipated amount of signal degradation over a transmission line. A digital-to-analog converter converts those certain waveforms into analog waveforms for transmission.
Wide-band replica output current sensing circuit
Granted: July 18, 2002
Application Number:
20020093366
An indirect current sensing circuit and method for replicating an output current is disclosed. The present invention is capable of preventing device damage and circuit disruption by maintaining output voltage signal integrity and consuming negligible power as well as optimizing output impedance. Furthermore, the indirect current sensing circuit and method is independent of semiconductor process variations and thus is more reliable over prior art current sensing techniques. The indirect…
Short circuit power limiter
Granted: July 11, 2002
Application Number:
20020089801
The present invention provides a short circuit power limiter circuit having a current sensor and a power limiter. The short circuit sensor sends a short circuit flag signal to the power limiter when the short circuit sensor detects a short circuit condition in a target circuit. The power limiter then reduces the power consumption of the target circuit. In a specific example, the power limiter toggles a particular portion of the target circuit on and off to reduce the circuit's average…
Clock recovery circuit
Granted: June 6, 2002
Application Number:
20020067788
A clock recovery circuit which has a transition detector connected to the incoming data stream. An output of the transition detector is connected to a gate, such as a D flip-flop, which has an input receiving the recovered clock. A zero or one output will be generated depending upon whether the transition is before or after the rising edge of the recovered clock. An accumulator circuit accumulates a count for each transition, providing the results to a comparison circuit. The comparison…
