Sound tracing method and device to improve sound propagation performance
Granted: September 24, 2024
Patent Number:
12101619
There is provided a sound tracing method. The method includes: a setup processing step of setting ray information; a ray generation step of generating a sound ray; a traversal/intersection test step of generating hit triangle information; a propagation path validation (PPV) step of searching a sound path; a guide plane sort step of generating and sorting a guide plane; a Reverb Geometry Collect/Reverb Plane Sort (RGC/RPS) step of generating and sorting a reverb plane; and an impulse…
Sound tracing apparatus and method
Granted: March 5, 2024
Patent Number:
11924626
Disclosed are a sound tracing apparatus and a sound tracing method, and the sound tracing apparatus includes a first acceleration structure generation unit configured to generate a first acceleration structure for a static scene in a sound space, an intersection test execution unit configured to perform an intersection test on each of a plurality of dynamic objects constituting a dynamic scene in the sound space to detect whether or not the dynamic object affects a sound propagation…
AC direct drive system for light emitting diodes with ultra-low flicker, low harmonic distortion, dimming compatibility and power line regulation
Granted: September 24, 2019
Patent Number:
10426008
As a non-limiting example, various aspects of this disclosure provide embodiments of AC direct drives for light emitting diodes for a wide variety of drive stages.
Adaptive body biasing in CMOS circuits to extend the input common mode operating range
Granted: September 17, 2019
Patent Number:
10418989
In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as…
Method and apparatus for multi-channel sensor interface with programmable gain, offset and bias
Granted: April 23, 2019
Patent Number:
10267662
A system supporting enhanced programmable signal adjustments may include a plurality of circuits configured to generate a corresponding plurality of input signals; a signal conditioner configured to condition the plurality of signals; and a controller configured to control the signal conditioner. The controller may generate one or more control signals for the controlling of the signal conditioner. The signal conditioner may select one or more input signals from the plurality of input…
AC direct drive system for light emitting diodes with ultra-low flicker, low harmonic distortion, dimming compatibility and power line regulation
Granted: February 5, 2019
Patent Number:
10201053
As a non-limiting example, various aspects of this disclosure provide embodiments of AC direct drives for light emitting diodes for a wide variety of drive stages.
Adaptive body biasing in CMOS circuits to extend the input common mode operating range
Granted: October 16, 2018
Patent Number:
10103728
In order to get the best of both high and low common mode ranges, an adaptive body biasing method using a pair of replica devices is implemented. Each replica device corresponds to a NMOS (or PMOS) device that constitutes the input pair used in a logic circuit or other type of integrated circuits. This configuration helps to increase the threshold voltage of the device, utilizing body effect, at high input common mode voltage, as desired for NMOS, and at low input common mode voltage, as…
Method and apparatus for multi-channel sensor interface with programmable gain, offset and bias
Granted: August 28, 2018
Patent Number:
10060773
Enhanced multi-channel sensor interfaces with programmable signal adjustments are provided. An example sensor interface may include an input selector that selects one or more sensor signals from a plurality of sensor signals based on input selection control signal; an offset generator that generates an offset signal based on an offset control signal; and a programmable signal adjuster that adjusts at least one selected sensor signal based on the generated offset signal and a signal…
Digital controlled oscillator based clock generator for multi-channel design
Granted: August 21, 2018
Patent Number:
10056890
A clock divider includes, in part, a pair of counters and a programmable delay line. A first one of the counters operates at a first frequency and is configured to count using a first integer portion of the divisor. The second counter operates at a second frequency smaller than the first frequency and is configured to count using a second integer portion of the divisor. The programmable delay line includes, in part, a chain of delay elements configured to generate a multitude of delays…
Method and apparatus for multi-channel sensor interface with programmable gain, offset and bias
Granted: November 28, 2017
Patent Number:
9829356
A highly integrated programmable sensor interface with improved sensor signal calibration and conditioning functions is described. The programmable sensor interface according to the present invention sensor interface provides programmable gain, digital offset correction and bias for one or more signal channels on one chip on a per channel basis. According to another aspect of the invention, the sensor interface provides reference voltage and sensor biasing by using an on-chip precision…
Recipient-driven traffic optimizing overlay systems and methods
Granted: July 11, 2017
Patent Number:
9705709
A data stream optimization system is configured to optimize the transfer of data using a plurality of relay nodes acting as the network overlay between a plurality of sources and a plurality of data requesting entities. As each data stream sent from a source to the data requesting entity passes through an relay node, the relay node optimizes network conditions and constraints based upon an identifying “signature” and priority conveyed by the requestor. The system is capable of…
Network data prioritizer
Granted: January 10, 2017
Patent Number:
9544242
A data packaging system is programmed to modify or otherwise manage a data stream from a data source prior to transmission to an intended recipient by applying an expressible intent regarding the data stream from the recipient in the form of a recipient signature. A data packager can apply a received recipient signature to modify the data stream based on the contents of the data stream. The modifications to the data stream can include prioritization of portions of the data stream…
All digital burst-mode clock and data recovery (CDR)
Granted: April 28, 2015
Patent Number:
9020087
The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase detector produces a late and an early comparison output. A block (digital filter) receives the late and early input and produces a multiplexer selector control signal. The phase selector multiplexer selects a clock phase as the recovered clock signal using multiplexer selector control signal.
Streaming and bulk data transfer transformation with context switching
Granted: October 21, 2014
Patent Number:
8868674
In described embodiments, processing of a data stream, such as a packet stream or flow, associated with data streaming is improved by context switching that employs context history. For each data stream that is transformed through processing, a context is maintained that comprises state information and includes a history and state information that enables the transformation for the data stream. Processing for the data transformation examines currently arriving data and then processes the…
Dejitter (desynchronize) technique to smooth gapped clock with jitter/wander attenuation using all digital logic
Granted: October 21, 2014
Patent Number:
8867682
Digital logic receives a gapped and jittery clock signal with specified frequency and frequency offset allowed by specification and a reference clock signal with same specified frequency and different frequency offset allowed by specification having low jitter. The digital logic adds and/or removes cycles from the reference clock signal over an extended period of time to produce a produced clock signal with low jitter that has a frequency that approaches the frequency of the gapped and…
Sequential electrostatic discharge (ESD)-protection employing cascode NMOS triggered structure
Granted: August 19, 2014
Patent Number:
8810981
An Electrostatic Discharge (ESD) protection circuitry comprises a protection device structure. The protection device structure includes at least one transistor with a gate operably connected to a pad. The at least one transistor turns on upon an ESD event and conducting charge to a substrate. At least one additional transistor with a gate operably connected to the substrate turns on after the at least one transistor upon an ESD protection event.
Sensorless self-tuning digital current programmed mode (CPM) controller with multiple parameter estimation and thermal stress equalization
Granted: September 17, 2013
Patent Number:
8536842
A multiphase controller for a DC-to-DC power supply includes logic to estimate parameters for multiple phases that provide a combined output at a load. The estimated parameters include a current estimate and an effective resistance estimates for each phase so that a power estimate for each phase can be produced. The logic adjusts the operation of the phases using the power estimate for each phase.
Digital pulse-frequency modulation controller for switch-mode power supplies with frequency targeting and ultrasonic modes
Granted: September 3, 2013
Patent Number:
8525502
A digital pulse controller uses digital logic to send pulses to a high side and low side switches of a switch-mode power supply converter. The digital logic uses a pulse frequency mode which includes a frequency targeting mode and an ultrasonic mode. The frequency targeting mode dynamically adjusts the size of the pulses in order to achieve a switching frequency within a desired band. The ultrasonic mode is switched into when the frequency of the pulses are at or below a threshold and…
Reference voltage based equivalent series resistance (ESR) emulation for constant on-time (COT) control of buck regulators
Granted: July 2, 2013
Patent Number:
8476882
The present invention uses a reference voltage that varies within a Pulse Width Modulation (PWM) cycle to generate the PWM signal. This allows for stability in the feedback of Constant On-Time (COT) control for buck controllers when low Equivalent Series Resistance (ESR) capacitors are used as the output capacitor. The reference voltage is adjusted using features of a PWM cycle in a voltage mode without using external inductor current information.
Digital boost feedback voltage controller for switch-mode power supplies using pulse-frequency modulation
Granted: January 29, 2013
Patent Number:
8362756
A controller produces high-side and low-side control signals. The high and low-side signals are used to switch high-side and low-side transistors in the power stage to control the voltage across the power stage output capacitor of the power stage. A boost feedback charge pump receives the low or high-side signal to increase the charge on a charge pump output capacitor. The controller is configured to send Pulse Frequency Modulation (PFM) high and low-side signals that control the voltage…
