Digital control method for improving heavy-to-light (step down) load transient response of switch mode power supplies
Granted: September 25, 2012
Patent Number:
8274264
A method for improving heavy-to-light load transient response in low-power switch-mode power supplies is described. It uses a negative voltage input power rail and a digital controller with an extended duty ratio control value to provide faster discharging current slew rate in the switched mode power supplies (SMPS) inductor.
Methodology for storing and updating on-chip revision level
Granted: June 26, 2012
Patent Number:
8209654
Logic to indicate a revision level includes multiple cells for one bit of the revision level. The cells being wired to be a pass-through cell or a swap cell during fabrication. At least some of the cells are such that to change the bit of the revision level, it is sufficient to change any single mask of a group of masks. The change to the single mask switches at least one of the cells from pass-through cell to a swap cell, or vice-versa.
System and method for data deduplication
Granted: June 19, 2012
Patent Number:
8205065
A system for deduplicating data comprises a card operable to receive at least one data block and a processor on the card that generates a hash for each data block. The system further comprises a first module that determines a processing status for the hash and a second module that discards duplicate hashes and their data blocks and writes unique hashes and their data blocks to a computer readable medium. In one embodiment, the processor also compresses each data block using a compression…
Output current and input power regulation with a power converter
Granted: June 5, 2012
Patent Number:
8193795
A power converter circuit senses the output voltage (Vo) and controls the converter's duty cycle (d1) to provide a steady output current (Io) or input power (Pin) in each switching cycle (T). During an initial period (Tramp), the controller provides a possibly smaller target current (Iramp) to reduce the system stress while the output voltage rises to a suitable value (InitVtar).
Methods, systems and computer program products for packet ordering for parallel packet transform processing
Granted: May 29, 2012
Patent Number:
8189591
Packets are processed while maintaining a sequence of the packets. Packets are received and a sequence identifier assigned to the packets. The sequence identifier specifies a serial order associated with the packet. The packets are provided to a plurality of parallel packet transform processors and the packets are processed utilizing the packet transform processors. The processed packets are ordered based on the sequence identifier of the packets. The packets may be evaluated to classify…
ESR zero estimation and auto-compensation in digitally controlled buck converters
Granted: February 14, 2012
Patent Number:
8115459
One embodiment of the present invention is a digitally controlled DC-DC converter comprising of a power stage including at least one switch and an output capacitor. A digital controller can control the switching of the at least one switch. The digital controller can include logic to produce an indication related to a zero resulting from the equivalent series resistance (ESR) of the output capacitor and to update the control of the switching of the switch in the power stage based on the…
Open-drain output buffer for single-voltage-supply CMOS
Granted: January 17, 2012
Patent Number:
8098090
An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains voltages greater than a predefined value. PMOS and NMOS well-bias selectors operate to select and provide an available highest or lowest voltage, respectively, to bias corresponding well-regions and ensure no device switching…
Self-tuning digital current estimator for low-power switching converters
Granted: December 27, 2011
Patent Number:
8085024
A switched mode power can use a digital controller to control the switching of the at least one switch of the switched mode power supply. The current through the power inductor can be estimated using a self-tuning digital current estimator.
Glue-logic based method and system for minimizing losses in oversampled digitally controlled DC-DC converters
Granted: December 20, 2011
Patent Number:
8081041
A practical method and system for oversampled digitally controlled DC-DC converters is presented. To minimize the switching losses while maintaining all advantages of the oversampling, “glue logic” and application specific oversampling digital pulse-width modulator are introduced. Experimental results demonstrate transient response with 50% smaller deviation than that of conventional controllers, allowing for proportional reduction in the size of the power stage output capacitor.
Low-voltage CMOS space-efficient 15 KV ESD protection for common-mode high-voltage receivers
Granted: June 28, 2011
Patent Number:
7969697
An electrostatic discharge protection device is disposed between true-complement input pins of a differential signal pair and a ground node. A common node couples the three diode stacks together. A first and a second diode stack each connect to one of the differential signal pair input pins. The third diode stack couples to the ground node. Each of the diode stacks is fabricated by a pair of high concentration p-type contact dopant regions within a low concentration n-well region. Each…
Multi-channel digital pulse width modulator (DPWM)
Granted: March 29, 2011
Patent Number:
7915938
A multiple channel Digital Pulse Width Modulator (DPWM) can include a single delay locked loop with a delay line, the delay line producing a number of outputs. Circuitry can use a delay line mask to mask a portion of the delay line outputs to produce a modified outputs so as to prevent premature pulse width reset. Jitter tolerance look ahead circuits can prevent jitter from causing premature reset of pulse width modulated signals. The pulse width modulators can include multiple…
Gray code current mode analog-to-digital converter
Granted: March 22, 2011
Patent Number:
7911366
One embodiment of the present invention is a Gray code current-mode analog to digital (ADC) converter using a Gray code current-mode ADC building block. The Gray code current-mode ADC building block can produce a Gray code bit and a current output that is sent to a next Gray code ADC building block. In one embodiment, the Gray code current-mode ADC building block does not use a voltage comparator in a signal path of the current output. In one embodiment, an 8 bit analog-to-digital…
System for storing encrypted data by sub-address
Granted: March 15, 2011
Patent Number:
7908473
A system and method for storing encrypted electronic data using a transmission Control Protocol (TCP), requires leaving both the header and the first 48 bytes of the “0” data packet in the data area of the TCP format in clear text. Consequently, the data can be routed to a main address (storage facility), and then to a sub-address (storage device) for storage. A single compression/encryption operation can be accomplished, before storage, at the host (server), the network switch, or…
Low power method of responsively initiating fast response to a detected change of condition
Granted: March 15, 2011
Patent Number:
7908508
A voltage signal is monitored in comparison to another voltage signal by a differential amplifier. When the first voltage signal value drops below the second voltage signal value an output signal is boosted in response. The output signal returns to a previous state without boost.
Combined full speed and high speed driver
Granted: March 8, 2011
Patent Number:
7902874
The separate high speed and full speed drivers used in a Universal Serial Bus 2.0 application can be combined into one driver which functions both as full speed/high speed driver and as a result provides output impedance for the full speed/high speed modes which is less process dependent.
Generating an encapsulating header based on encapsulated information provided at protocol-dependent locations
Granted: January 18, 2011
Patent Number:
7873045
An encapsulation packet is received as a sequence of parallel data segments. First information within the encapsulated packet is obtained based on second information indicative of a location of the first information within the encapsulated packet. The encapsulating header is modified based on the first information.
Low power charge pump
Granted: November 16, 2010
Patent Number:
7834672
A charge pump is configured to control current flow at an output node in response to input signals. A plurality of control signals are generated based upon the input signals. The control signals operate to control the timing and duration of current flows within the charge pump and to thereby reduce charge pump power consumption. Based upon the control signals, the conductivity of a first path between a power supply and the output node and a second path between the output node and a…
Universal and fault-tolerant multiphase digital PWM controller for high-frequency DC-DC converters
Granted: October 26, 2010
Patent Number:
7821431
A multiphase hybrid digital pulse width modulator can comprise a counter that is selectable between at least two different numbers of states to indicate a first portion of a switching period. Unclocked logic can indicate a second portion of the switching period. The unclocked logic can include a delay line.
Means to reduce the PLL phase bump caused by a missing clock pulse
Granted: October 19, 2010
Patent Number:
7816958
A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and applied to the charge pump during a first period. The detection of the pulse-width limited signal is used to generate a first slew signal that is also pulse-width limited and applied to the charge pump during a second period.…
Method and apparatus for frame delineation
Granted: October 12, 2010
Patent Number:
7814376
A frame delineation mechanism which alternately considers even and odd sync pattern position possibilities. With the addition of toggle logic, each of 66 possible states of even and odd alignment are exhausted in turn, odd, followed by even, followed by odd and so on, providing synchronization more quickly than known mechanisms. Additionally, faster convergence is reached due to the use of an exhaust register which keeps track of those alignment states that were tested but did not…
