Programmable differentiator delay
Granted: July 20, 1993
Patent Number:
5229664
A programmable delay for the gate signal output of the differentiator in a data analyzing circuit is provided. A data signal is produced by a low pass filter, and a differentiator (high pass filter) produces a gate signal. The cutoff frequency of the low pass filter is controlled by a first control circuit, and a second control circuit is provided to separately control the cutoff frequency of the high pass filter. The second control circuit produces a variation from the base frequency…
Method of making vertical PNP transistor
Granted: March 2, 1993
Patent Number:
5190884
A vertical PNP transistor for use in an integrated circuit is disclosed. A P-type substrate serves as collector. An N-type epitaxial layer is formed on the substrate and serves as base. A P-type region is formed in the epitaxial layer and serves as emitter. An N.sup.+ -type localized buried layer is formed on the substrate in the area beneath the emitter. The localized buried layer covers less than all of the area under the emitter. An N.sup.+ -type sinker region is formed through the…
Reactor for epitaxial growth
Granted: October 6, 1992
Patent Number:
5152842
A reactor for epitaxial growth wherein a susceptor on which semiconductor wafers are placed is heated by a heater, while rotating around a vertically provided gas feed pipe in a bell jar and a gas introduced through the gas feed pipe into the bell jar is decomposed to deposite a crystalline semiconductor material on the wafers, the susceptor having a plurality of pockets for positioning the wafers in which the pockets are arranged on the uniform temperature region of the susceptor other…
Dual EEPROM cell with current mirror differential read
Granted: September 15, 1992
Patent Number:
5148395
An EEPROM device having dual EEPROM transistor blocks for storing a charge and a current mirror for determining the difference in charge between the EEPROM transistor blocks. During a write operation, one EEPROM transistor block is charged while the other block is discharged. During a read operation, the current mirror attempts to supply equal current to each of the EEPROM transistor blocks. However, because each block has a different charge, more current will be forced through one leg…
Vertical PNP transistor
Granted: March 17, 1992
Patent Number:
5097309
A vertical PNP transistor for use in an integrated circuit is disclosed. A P-type substrate serves as collector. An N-type epitaxial layer is formed on the substrate and serves as base. A P-type region is formed in the epitaxial layer and serves as emitter. An N.sup.+ -type localized buried layer is formed on the substrate in the area beneath the emitter. The localized buried layer covers less than all of the area under the emitter. An N.sup.+ -type sinker region is formed through the…
Programmable transistor
Granted: November 26, 1991
Patent Number:
5068702
An improved cell structure and method for making the same for semicustom chips which can be connected at the metalization step to form either an NPN or a PNP transistor and which has approximately the same cell size as a single PNP or NPN transistor. A central P-doped region forms the emitter of the PNP transistor. This is partially surrounded by another P-doped region which forms the collector of the PNP transistor. An N-doped region is diffused into one of the P-doped regions to form…
Method of making a multicollector vertical pnp transistor
Granted: June 11, 1991
Patent Number:
5023194
A vertical semiconductor device having a plurality of vertical active regions and a method for manufacturing such a vertical semiconductor device. In the preferred embodiment, a vertical multicollector pnp transistor is formed by disposing a plurality of n type epitaxial layers over a bottom p type substrate. Each epitaxial layer has a plurality of collector regions formed therein. The collector regions are connected using a single diffusion step to form vertical collectors for the pnp…
Programmable die size continuous array
Granted: May 14, 1991
Patent Number:
5016080
The present invention covers a semiconductor wafer for semi-custom use in which there are no scribe lines in at least one direction. Electrically isolated cells are provided throughout the wafer. The scribe lines can thus be arbitrarily placed according to an individual customer's instructions, with the isolated cells near the scribe line being covered with metalization to form a bonding pad. Preferably, scribe lines are provided in one direction, either horizontal or vertical. This…
Method of making a complementary BiCMOS process with isolated vertical PNP transistors
Granted: April 30, 1991
Patent Number:
5011784
A BiCMOS process which provides both isolated and vertical NPN and PNP transistors with better performance characteristics and fewer additional steps than the prior art. The additional steps consist of masked implants with no changes in the thermal steps of the CMOS process. An N-well to contain the vertical PNP transistor is formed during the same step that the NPN vertical transistor collector is formed. The N base of the PNP transistor is formed by implanting an N type material. A P…
Programmable bonding pad with sandwiched silicon oxide and silicon nitride layers
Granted: August 14, 1990
Patent Number:
4949150
The present invention is a bonding pad structure and method for making the same which can be connected at the metalization step to form passive or active devices in addition to forming a bonding pad. A P-doped region is formed in an epitaxial layer in the area of the bonding pad at the perimeter of a chip. This P-doped region allows the formation of a junction capacitance between it and the epitaxial layer. In addition, by adding an oxide layer over the P-doped region an oxide capacitor…
Wideband 0-90 degrees adjustable phase shifter
Granted: September 12, 1989
Patent Number:
4866397
The present invention is an improved phase shift circuit for a recovered clock signal used to recover data which provides an adjustable 90 degrees phase shift using a linear, constant current charge without requiring an external capacitor for integrated receivers and repeaters. A pair of differential transistors receive an input signal and produce an output with a capacitor coupled between their output electrodes. A pair of switching transistors are coupled between the output electrodes…
Programmable active/passive cell structure
Granted: July 25, 1989
Patent Number:
4851893
An improved cell structure which can be programmed to have resistors, an NPN transistor or a PNP lateral transistor in a linear arrangement with an open PNP structure. The PNP collector regions are made parallel to a PNP emitter, with lightly doped resistive P-regions attached to the ends of the emitter region to prevent the flow of current to the P-isolation boundary region. At least one base region is provided in line with a collector region and adjacent one of the resistive regions…
PSK digital echo modulator with reduced memory capacity required
Granted: October 14, 1986
Patent Number:
4617535
An improved method and apparatus for reducing the amount of memory required to implement a digital echo modulator. A single permanent memory stores digital representations of a series of samples of a signal element for several phases of the signal element. A temporary memory is provided to store the digital representations from a plurality of signal elements to be overlapped. The signal element values are clocked out of the permanent memory and into the temporary memory at a rate, during…
