Pipelined analog to digital converter
Granted: November 5, 1996
Patent Number:
5572212
A pipelined analog to digital converter in which data samples ripple down through the pipeline of comparator stages. Each stage of the pipeline includes switch capacitor amplifiers for comparing an analog signal to a first reference voltage, to a second reference voltage, and to an average of the first and second reference voltages. Fan out of circuit components can be eliminated in succeeding stages, and error correction is provided by including overlapping of ranges passed by an…
Transconductor element for high speed GM-C integrated filters
Granted: October 29, 1996
Patent Number:
5570049
A circuit technique for improving high frequency performance of current-controlled transconductor elements in transconductance-capacitance (g.sub.m -C) based monolithic filters. The circuit detects the output impedance of the transconductance transistors inside the transconductor element, regenerates and applies a negative conductance to the output of the transconductor. By cancelling the transistor output impedance, the total differential mode output impedance of the transconductor…
NRZ to RLL encoder circuit in disk drive read/write channel
Granted: September 17, 1996
Patent Number:
5557481
An encoder circuit in the read/write channel of a disk drive encodes NRZ data from a host computer into RLL data to be stored in the disk drive even at high frequencies of the RLL clock. Serial NRZ input data is first converted into two parallel NRZ data signals. The second NRZ signal is delayed by one clock cycle with respect to the first NRZ signal. A clock derived from the NRZ clock signal clocks the parallel NRZ signals through a first stage of flip-flops. An RLL clock signal then…
High speed divide by 1.5 clock generator
Granted: September 3, 1996
Patent Number:
5552732
A simple, reliable, divide by 1.5 clock generator is provided. This is done by using a divide by 3 circuit with three gates. The first two gates are clocked by the RLL clock, and the third gate is clocked by the inverse of the RLL clock. The output of the first gate is combined with the RLL clock to provide an output pulse. Another output is produced when the output of the third gate is combined with the inverse of the RLL clock. The combination of these two outputs thus produces a…
Speakerphone with event driven control circuit
Granted: August 6, 1996
Patent Number:
5544242
A control circuit for a speakerphone circuit which utilizes an event driven circuit to determine the appropriate gain for the receive and transmit channels is provided. Detectors monitor the relative magnitudes of the signal in the transmit and receive channels. Separate signal-to-noise detectors determine whether signals present in the two channels are voice signals. The event driven circuit receives these inputs, and dependent on the present state (i.e., transmit, receive, or idle)…
Low-voltage cascaded current mirror circuit with improved power supply rejection and method therefor
Granted: April 30, 1996
Patent Number:
5512816
A circuit technique for improving power supply rejection of current mirror circuits. An input reference current is mirrored through a cascade of current mirror circuits whereby an error current is generated that represents the amount of current variation caused by power supply variations. The error current is then replicated into a current summing circuit which cancels out the effect of the error current. The output current is thus substantially independent of power supply variations.
Output limiter for class-D BICMOS hearing aid output amplifier
Granted: April 9, 1996
Patent Number:
5506532
An invention providing a hard limiter between the pulse width modulator and output drive transistors of a class-D amplifier is disclosed. The limiter functions by controlling the duty cycle of the pulse width modulator output, which directly corresponds to the magnitude of the voltage appearing across the load output transducer. The pulse width modulated (PWM) signal is compared to the outputs of a pair of one-shot circuits (single pulse generators). If either the positive pulse or the…
Dual stage differential adaptive peak detector for data communications receivers
Granted: March 26, 1996
Patent Number:
5502746
A dual stage adaptive peak detect circuit includes a fast peak detector that detects the trends in the magnitude of the incoming signal and an adaptable peak detector that accurately follows the peak of the signal. A difference circuit detects the voltage difference between the outputs of the fast peak detector and the adaptable peak detector. A voltage-to-current converter feeds back the current-converted difference voltage to the adaptable peak detector to adjust its peak detection…
Small form factor atomizer
Granted: September 26, 1995
Patent Number:
5452711
A reduced form factor atomizer is disclosed comprised of a control electronics module and a dosage/transducer module designed for ultra-compact usage to provide a small and compact form factor. The dosage/transducer module includes a read only memory containing parameters associated with the fluid to be atomized in the module. In use, the two modules are mated together to form the small and compact form factor and include one of a male and female connector to couple the control…
Continuously linear pulse amplifier/line driver with large output swing
Granted: August 29, 1995
Patent Number:
5446412
A transmission line driver circuit for use in data communication transmitters that is capable of meeting the return loss specifications as well as the electrical interface specifications as defined by C.C.I.T.T. standards for E1/T1 transmission. The line driver circuit of the present invention maintains minimum output impedance during the entire dynamic range of the transmit signal while meeting the pulse shape template requirements. The circuit includes a predriver stage that controls…
Accurate low voltage detect circuit
Granted: August 8, 1995
Patent Number:
5440254
An accurate and stable low voltage detect circuit that provides a low voltage detect signal with minimal variation over process and temperature without trimming requirements. The power supply voltage is divided by a resistor voltage divider and compared to the output voltage of a bandgap reference circuit at the inputs of a comparator. The output of the comparator indicates power-on when the voltage divided power supply raises above the bandgap reference voltage. The low voltage detect…
Output limiter for class-D BICMOS hearing aid output amplifier
Granted: February 14, 1995
Patent Number:
5389829
An invention providing a hard limiter between the pulse width modulator and output drive transistors of a class-D amplifier is disclosed. The limiter functions by controlling the duty cycle of the pulse width modulator output, which directly corresponds to the magnitude of the voltage appearing across the load output transducer. The pulse width modulated (PWM) signal is compared to the outputs of a pair of one-shot circuits (single pulse generators). If either the positive pulse or the…
Voltage controlled attenuator for speakerphones
Granted: February 7, 1995
Patent Number:
5387877
An integrated circuit voltage controlled attenuator which reduces control voltage feedthrough by employing NPN transistors for both sets of current steering elements is disclosed. A pair of emitter coupled NPN transistors are provided, connected to a common current source. The collector currents of these transistors form input currents of two precision PNP current mirrors. Output currents from the mirrors are coupled to a second pair of emitter coupled NPN transistors, having a current…
Read/write circuit with switchable head resistance for read and write modes
Granted: October 18, 1994
Patent Number:
5357379
A read/write circuit for a disk drive system with a two-terminal magnetic head, having an adjustable damping resistor across the magnetic head. A switch network connects across the magnetic head and controls a resistor network to obtain an optimum level of impedance across the magnetic head in both the read mode and the write mode. The circuit provides a lower and well-defined impedance across the magnetic head in the write mode for all operating voltages across the head. A clamp circuit…
Low voltage CMOS bandgap with new trimming and curvature correction methods
Granted: June 28, 1994
Patent Number:
5325045
A bandgap circuit for generating an accurate and stable reference voltage at low power supply voltages. Stacking of bipolar devices allows for a lower opamp closed-loop gain, which in turn reduces the error voltage contribution to the output due to opamp offset. A CMOS opamp having NMOS input reference transistors coupled with a new bandgap architecture allows a 1.2 v reference (unlike other stacked architectures) without sacrificing low voltage operation. A new trimming method provides…
CMOS opamp with large sinking and sourcing currents and high slew rate
Granted: June 28, 1994
Patent Number:
5325069
A CMOS opamp having large sinking and sourcing currents, and capable of driving high capacitive loads. The CMOS opamp improves a prior art OPAMP that includes a folded cascode gain stage and a class A/B output stage. By inserting a source follower stage between the folded cascode stage and the output stage, the opamp can drive very large capacitive loads that can also compensate the opamp. By further modifying the output stage, the ability to sink load current is vastly improved.
Control circuit for voltage controlled attenuator for speakerphones
Granted: June 7, 1994
Patent Number:
5319704
An integrated control circuit for generating a regulated control voltage for voltage-controlled attenuators used in speakerphone circuits. The circuit provides separate transmit and receive voltage regulation to provide accurate gain settings for the voltage-controlled attenuators. The circuit eliminates the need for absolute value external components or external signal feedback between the voltage-controlled attenuators and the control circuit.
Rail-to-rail opamp with large sourcing current and small quiescent current
Granted: May 24, 1994
Patent Number:
5315264
A rail-to-rail CMOS operational amplifier with a large source current and small quiescent current. The CMOS opamp includes a folded cascode input structure, a negative slew detector and an output stage that acts as a push-pull output stage during slewing and a Class A output stage during small signal operation. The opamp can drive large capacitive loads (in excess of 0.5 .mu.F), with the load capacitor providing for the opamp frequency compensation.
Method of making isolated vertical PNP transistor in a complementary BICMOS process with EEPROM memory
Granted: September 28, 1993
Patent Number:
5248624
A method and apparatus for an improved isolated vertical PNP in a complementary BICMOS process with EEPROM memory is provided. The isolated vertical PNP transistor is formed on a P-substrate with a P-epitaxial (EPI) layer. The collector of the vertical PNP transistor is isolated with an N- buried layer formed in the P substrate and an N+ buried layer on the sidewalls for isolation. The collector is formed with a P+ layer buried in the N- layer. Subsequently, the P- EPI layer is deposited…
Class-d BICMOS hearing aid output amplifier
Granted: September 21, 1993
Patent Number:
5247581
An invention, which is fabricated using a Bipolar and Complementary Metal Oxide Semiconductor (BICMOS) technology which offers both bipolar and CMOS devices on the same silicon substrate is disclosed. The major part of the internal circuitry uses bipolar devices while the output circuit driving the transducer at the output uses CMOS inverters. A voltage regulator which is fed from the battery lines is used to power the majority of the internal circuitry leaving only the CMOS output…
