Surface mountable optocoupler package
Granted: March 6, 2003
Application Number:
20030042403
An optocoupler package is disclosed. The optocoupler package comprises a carrier substrate and a plurality of conductive regions on the carrier substrate. An optoelectronic device, an optically transmissive medium, and a plurality of conductive structures can be on the carrier substrate.
Method and circuit for reducing losses in DC-DC converters
Granted: February 27, 2003
Application Number:
20030038615
In accordance with the present invention, a switching converter includes two transistors Q1 and Q2 parallel-connected between two terminals. Transistor Q1 is optimized to reduce the dynamic loss and transistor Q2 is optimized to reduce the conduction loss. Q1 and Q2 are configured and operated such that the dynamic loss of the converter is dictated substantially by Q1 and the conduction loss of the converter is dictated substantially by Q2. Thus, the tradeoff between these two types of…
Packaged semiconductor device and method of manufacture using shaped die
Granted: February 6, 2003
Application Number:
20030025183
A semiconductor packaging technique provides for a semiconductor device with improved electrical and thermal performance. According to one embodiment of the invention, die edges are shaped before encapsulation to move the peripheral area of the die, which is more susceptible to stress and cracking, further inside the molding compound. This results in a device that can better withstand stress as well being more resistant to corrosion and other reliability problems caused by environmental…
Unmolded package for a semiconductor device
Granted: January 16, 2003
Application Number:
20030011005
A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while…
Power module package having improved heat dissipating capability
Granted: January 16, 2003
Application Number:
20030011054
A power module package is provided. The power module package includes a power circuit element, a control circuit element, a lead frame, a heat sink, and an epoxy molding compound (EMC). The control circuit element is connected to the power circuit and controls chips in the power circuit. The lead frame has external connecting means formed at the edges thereof, and a down set part, namely, formed between the external connecting means. The lead frame has a first surface to which the power…
Method and circuit for performing automatic power on reset of an integrated circuit
Granted: January 16, 2003
Application Number:
20030014620
Method and circuitry for automatic resetting of an integrated circuit upon power up handles multiple clock sources and minimizes power dissipation. A robust voltage sensing circuit detects power up and triggers resetting of most of the circuit with the exception of the initialization circuit that includes an internal oscillator. After the circuit determines that the internal oscillator signal has settled, contents of non-volatile register are read to select the clock source for the…
Power MOS device with improved gate charge performance
Granted: December 19, 2002
Application Number:
20020190282
A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the…
MOS-gated power device with doped polysilicon body and process for forming same
Granted: November 28, 2002
Application Number:
20020175383
An improved MOS-gated power device 300 with a substrate 101 having an upper layer 101a of doped monocrystalline silicon of a first conduction type that includes a doped well region 107 of a second conduction type. The substrate further includes at least one heavily doped source region 111 of the first conduction type disposed in a well region 107 at an upper surface of the upper layer, a gate region 106 having a conductive material 105 electrically insulated from the source region by a…
System to enable photolithography on severe structure topologies
Granted: November 14, 2002
Application Number:
20020168589
A system and related process to enable control of photolithographic pattern features on a structure having one or more severe non-flat topologies. The system includes an analysis of the Depth of Focus associated with photolithographic equipment and a photoresist film applied to the structure. From that determination a range of layout dimension of the topologies is identified accordingly and incorporated into the fabrication of such topologies. A conformal layer of material is then…
Mid-connect architecture with point-to-point connections for high speed data transfer
Granted: October 31, 2002
Application Number:
20020162083
A mid-connect interconnection system for coupling a plurality of function cards to one another via a plurality of switch cards. The connection may be established using direct connectors of very short length to provide high-speed transmission with little to no reflection concerns. The connectors are arranged such that the function cards are not connected in parallel with the switch cards. The mid-connect arrangement provides connector access points or locations corresponding in number to…
Method for creating thick oxide on the bottom surface of a trench structure in silicon
Granted: October 24, 2002
Application Number:
20020153557
A gate isolation structure of a semiconductor device and method of making the same provides a trench in a silicon substrate, wherein a dielectric layer is formed on sidewalls and bottom of the trench, the dielectric layer having a first thickness on the sidewalls and a second thickness at the bottom that is greater than the first thickness. The thicker dielectric layer at the bottom substantially reduces gate charge to reduce the Miller Capacitance effect, thereby increasing the…
Packaging system for die-up connection of a die-down oriented integrated circuit
Granted: October 3, 2002
Application Number:
20020140070
A die attach package for connecting a die or chip of die-down orientation to a printed circuit board in a die-up orientation. The package includes a substrate with leads that may be traces terminating in vias or that may be the leads of a lead frame. The traces or the leads of the lead frame are modified such that they pass under the die when the die is attached. The traces or leads are routed under the die such that proper connections are established from the topside of the die to the…
Method of forming a trench transistor having a superior gate dielectric
Granted: August 1, 2002
Application Number:
20020100932
A trench transistor with lower leakage current and higher gate rupture voltage. The gate oxide layer of a trench transistor is grown at a temperature above about 1100° C. to reduce thinning of the oxide layer at the corners of the trench. In a further embodiment, a conformal layer of silicon nitride is deposited over the high-temperature oxide layer, and a second oxide layer is formed between the silicon nitride layer and the gate polysilicon. The first gate oxide layer, silicon…
Trench MOSFET formed using selective epitaxial growth
Granted: August 1, 2002
Application Number:
20020102786
A method of creating a thermally grown oxide of any thickness at the bottom of a silicon trench. A dielectric (e.g. oxide) pillar of a predetermined thickness is formed on a semiconductor substrate. A selective epitaxial growth (SEG) process is used to form an epitaxial layer around and over the oxide pillars. A trench is patterned and etched through the SEG layer and in alignment with the oxide pillar such that the trench terminates at the top of the oxide pillar.
Metal gate double diffusion MOSFET with improved switching speed and reduced gate tunnel leakage
Granted: July 4, 2002
Application Number:
20020084486
A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor (10) with a metal gate (26). A sacrificial gate layer is patterned to provide a self-aligned source mask. The source regions (20) are thus aligned to the gate (26), and the source diffusion provides a slight overlap (28) for good turn-on characteristics and low leakage. The sacrificial gate layer is capable of withstanding the diffusion temperatures of the DMOS process and is selectively etchable.…
Flip chip in leaded molded package with two dies
Granted: June 6, 2002
Application Number:
20020066950
A chip device including two stacked dies. The chip device includes a leadframe that includes a plurality of leads. A first die is coupled to a first side of the leadframe with solder and a second die is coupled to a second side of the leadframe with solder. A molded body surrounds at least a portion of the leadframe and the dies.
Power mosfet and method for forming same using a self-aligned body implant
Granted: January 24, 2002
Application Number:
20020008284
A method for making a power MOSFET includes forming a trench in a semiconductor layer, forming a gate dielectric layer lining the trench, forming a gate conducting layer in a lower portion of the trench, and forming a dielectric layer to fill an upper portion of the trench. Portions of the semiconductor layer laterally adjacent the dielectric layer are removed so that an upper portion thereof extends outwardly from the semiconductor layer. Spacers are formed laterally adjacent the…
High frequency MOSFET switch
Granted: July 12, 2001
Application Number:
20010007430
A high-frequency switch circuit having an MOS pass gate or transfer transistor. The switch circuit of the invention includes a first impedance element coupled to the gate of the transfer transistor and, preferably, an alternative second impedance element coupled to the bulk of the transfer transistor. One or both of the impedance elements substantially negates the low-parasitic shunt capacitance associated with the transfer transistor that controls signal attenuation under high frequency…
