Power chip scale package
Granted: July 8, 2004
Application Number:
20040130011
A packaging arrangement for a semiconductor device including a leadframe and a die coupled thereto. The die is coupled to the leadframe such that its back surface (drain area) is coplanar with source leads and a gate lead extending from the leadframe. A stiffener is coupled to the leadframe and electrically isolated therefrom in order to help maintain the position of the source and gate pads of the leadframe. When the semiconductor device is coupled to a printed circuit board (PCB), the…
MULTICHIP MODULE INCLUDING SUBSTRATE WITH AN ARRAY OF INTERCONNECT STRUCTURES
Granted: July 1, 2004
Application Number:
20040125573
A multichip module is disclosed. In one embodiment, the multichip module includes a substrate having a first side and a second side, the first side being opposite to the first side. A driver chip is at the first side of the substrate. A semiconductor die comprising a vertical transistor is at the second side of the substrate. The driver chip and the semiconductor die are in electrical communication through the substrate.
Trench structure having one or more diodes embedded therein adjacent a PN junction and method of forming the same
Granted: May 6, 2004
Application Number:
20040084721
In accordance with an embodiment of the invention, a semiconductor structure includes a semiconductor region having a P-type region and a N-type region forming a PN junction therebetween. A first trench extends in the semiconductor region adjacent at least one of the P-type and N-type regions. The first trench includes at least one diode therein.
Semiconductor die package including drain clip
Granted: April 1, 2004
Application Number:
20040063240
One embodiment of the invention is directed to a semiconductor die package including a semiconductor die comprising a first surface, a second surface, and a vertical power MOSFET having a gate region and a source region at the first surface a drain region at the second surface. A drain clip having a major surface is electrically coupled to the drain region. A gate lead is electrically coupled to the gate region. A source lead is electrically coupled to the source region. A non-conductive…
Flip chip in leaded molded package and method of manufacture thereof
Granted: March 25, 2004
Application Number:
20040056364
A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.
Substrate based unmolded package including lead frame structure and semiconductor die
Granted: March 4, 2004
Application Number:
20040041242
A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.
DUAL TRENCH POWER MOSFET
Granted: February 5, 2004
Application Number:
20040021173
In accordance with an embodiment of the present invention, a MOSFET includes a first semiconductor region of a first conductivity type, a gate trench which extends into the first semiconductor region, and a source trench which extends into the first semiconductor region. The source trench is laterally spaced from the gate trench.
Soft start techniques for control loops that regulate DC/DC converters
Granted: February 5, 2004
Application Number:
20040022078
Improved soft start techniques for control loops that regulate DC/DC converter circuits are provided. An improved soft start circuit provides a varying voltage at the output of an error amplifier in the control loop during the start-up phase of the DC/DC converter. The varying voltage generated by an improved soft start circuit is related to the amplitude of the saw-tooth ramp signal that controls the switching duty cycle. The varying voltage generated by an improved soft start circuit…
Vertical charge control semiconductor device
Granted: January 22, 2004
Application Number:
20040014451
In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer periphery of each of the two insulation-filled trench regions. A ratio of a width of each of the insulation-filled trench regions to a width of the drift region is adjusted so that an output capacitance of the MOSFET is…
Flip chip with solder pre-plated leadframe including locating holes
Granted: September 25, 2003
Application Number:
20030178717
A flip-chip with a solder pre-plated leadframe that includes locating holes. The leadframe does not include a die attach pad. Two of the leads include a locating or alignment hole for receiving a solder bump of the bumped die. The remaining leads include die contact areas for placement of the die thereon with the solder bumps contacting the die contact areas. The leads with the die contact areas are downset. The downset is approximately 4 mm.
Semiconductor die package with semiconductor die having side electrical connection
Granted: July 24, 2003
Application Number:
20030139020
A semiconductor die package is disclosed. In one embodiment, the semiconductor die package includes a circuit substrate including a conductive region. A semiconductor die is on the circuit substrate. The semiconductor die includes an edge and a recess at the edge. A solder joint couples the semiconductor die and the conductive region through the recess.
Field effect transistor and method of its manufacture
Granted: July 10, 2003
Application Number:
20030127688
A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the…
High performance multi-chip flip chip package
Granted: July 3, 2003
Application Number:
20030122247
A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon…
Device authentication system and method
Granted: June 26, 2003
Application Number:
20030120922
A system and method for device authentication are disclosed. In one embodiment, a random security code is generated during a boot operation to verify authenticity of a device. The random security code may comprise a rolling code based on a static number and a seed number, where the static number does not change between successive boots and the seed number changes between boots. A random number generator algorithm may provide the seed number.
High performance multi-chip flip chip package
Granted: June 12, 2003
Application Number:
20030107126
A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon…
Semiconductor power package module
Granted: May 8, 2003
Application Number:
20030085456
A semiconductor power module in which a power circuit chip and a control circuit chip are integrated in a package, is provided. The semiconductor power module includes a case; a terminal inserted into the case, the terminal including portions protruding upward to the outside of the case, and portions exposed in the case; a first substrate to which the power circuit chip is attached, the first substrate attached to the case for encapsulating the bottom of the package; a second substrate…
Semiconductor packages for semiconductor devices
Granted: May 8, 2003
Application Number:
20030085464
A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die having a vertical power transistor, a first surface and a second surface. A ground plane proximate the second surface and distal to the first surface. A bus member covers a portion the first surface of the semiconductor die and has at least one leg that electrically couples a source region of the semiconductor die to the ground plane.
Thin, thermally enhanced flip chip in a leaded molded package
Granted: April 24, 2003
Application Number:
20030075786
Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead…
Semiconductor structure with improved smaller forward voltage loss and higher blocking capability
Granted: April 17, 2003
Application Number:
20030073287
A semiconductor device is disclosed. The semiconductor device includes one or more charge control electrodes a plurality of charge control electrodes. The one or more charge control electrodes may control the electric field within the drift region of a semiconductor device.
Semiconductor device including molded wireless exposed drain packaging
Granted: March 20, 2003
Application Number:
20030052408
A semiconductor device including a leadframe and a die coupled thereto. A drain pad is coupled to the drain region of the die in a body that substantially envelopes the leadframe and the die. The body includes a window defined therein. The body is placed around the leadframe and the die such that a surface of the drain pad opposite the die is exposed through the window.
