Adjustment mechanism
Granted: May 6, 2008
Patent Number:
7368930
A probe card assembly can comprise a support structure to which a plurality of probes can be directly or indirectly attached. The probes can be disposed to contact an electronic device to be tested. The probe card assembly can further comprise actuators, which can be configured to change selectively an attitude of the support structure with respect to a reference structure. The probe card assembly can also comprise a plurality of lockable compliant structures. While unlocked, the…
Isolation buffers with controlled equal time delays
Granted: April 22, 2008
Patent Number:
7362092
A system is provided for controlling the delay in an isolation buffer. Multiple such isolation buffers are used to connect a single signal channel to multiple lines and controlled to provide an equal delay. Isolation buffer delay is controlled to be uniform by varying either power supply voltage or current. A single delay control circuit forming a delay-lock loop supplies the delay control signal to each buffer to assure the uniform delay. Since controlling delay can also vary the output…
Probe card assembly and kit
Granted: April 1, 2008
Patent Number:
7352196
In a probe card assembly, a series of probe elements can be arrayed on a silicon space transformer. The silicon space transformer can be fabricated with an array of primary contacts in a very tight pitch, comparable to the pitch of a semiconductor device. One preferred primary contact is a resilient spring contact. Conductive elements in the space transformer are routed to second contacts at a more relaxed pitch. In one preferred embodiment, the second contacts are suitable for directly…
Contact carriers (tiles) for populating larger substrates with spring contacts
Granted: March 25, 2008
Patent Number:
7347702
An interconnection apparatus and a method of forming an interconnection apparatus. Contact structures are attached to or formed on a first substrate. The first substrate is attached to a second substrate, which is larger than the first substrate. Multiple such first substrates may be attached to the second substrate in order to create an array of contact structures. Each contact structure may be elongate and resilient and may comprise a core that is over coated with a material that…
Wafer-level burn-in and test
Granted: March 18, 2008
Patent Number:
7345493
Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly…
Method of probing a device using captured image of probe structure in which probe tips comprise alignment features
Granted: March 11, 2008
Patent Number:
7342402
An image of an array of probes is searched for alignment features. The alignment features are then used to bring contact targets and the probes into contact with one another. The alignment features may be a feature of one or more of the tips of the probes. For example, such a feature may be a corner of one of the tips. An array of probes may be formed to have such alignment features.
Apparatus for reducing power supply noise in an integrated circuit
Granted: March 11, 2008
Patent Number:
7342405
A power supply provides power to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal may temporarily increase due, for example, to state changes in the DUT. To limit variation (noise) in voltage at the power input terminal, a supplemental current is supplied to the power input terminal.
High density planar electrical interface
Granted: February 26, 2008
Patent Number:
7335057
An apparatus including a substrate having a plurality of through holes and a plurality of cables, including wires and/or coaxial cables, extending through respective ones of the plurality of through holes of the substrate. Each of the cables comprises a conductor and terminates about a surface of the substrate such that the conductors of respective ones of plurality of cables are planarly aligned and available for electrical contact. A system including a cable interface extending through…
Method for making a socket to perform testing on integrated circuits
Granted: February 12, 2008
Patent Number:
7330039
A interconnect structure is inexpensively manufactured and easily insertable into a socket. The interconnect structure is manufactured by forming a sacrificial substrate with cavities that is covered by a masking material having openings corresponding to the cavities. A first plating process is performed by depositing conductive material, followed by coupling wires within the openings and performing another plating process by depositing more conductive material. The interconnect…
Rhodium electroplated structures and methods of making same
Granted: February 5, 2008
Patent Number:
7326327
A halide based stress reducing agent is added to the bath of a rhodium plating solution. The stress reducing agent reduces stress in the plated rhodium, increasing the thickness of the rhodium that can be plated without cracking. In addition, the stress reducing agent does not appreciably decrease the wear resistance or hardness of the plated rhodium.
Method of forming an interconnection element
Granted: February 5, 2008
Patent Number:
7325302
A method of forming an interconnection element. In one embodiment, the interconnection element includes a first structure and a second structure coupled to the first structure. The second structure coupled with the first material has a spring constant greater than the spring constant of the first structure alone. In one embodiment, the interconnection element is adapted to be coupled to an electronic component tracked as a conductive path from the electronic component. In one embodiment,…
Method and system for compensating thermally induced motion of probe cards
Granted: December 25, 2007
Patent Number:
7312618
A method and system for compensating for thermally induced motion of probe cards used in testing die on a wafer are disclosed. A probe card incorporating temperature control devices to maintain a uniform temperature throughout the thickness of the probe card is disclosed. A probe card incorporating bi-material stiffening elements which respond to changes in temperature in such a way as to counteract thermally induced motion of the probe card is disclosed including rolling elements, slots…
Method and device to clean probes
Granted: December 11, 2007
Patent Number:
7306849
A probe cleaning system automatically detects a surface of a probe cleaning device during a cleaning process by providing a predetermined finish on the surface of the probe cleaning device. The predetermined finish can include a textured or machined finish or a marking, such that the predetermined finish provides contrast against the surface. Cameras in the system automatically focus on the surface, with the predetermined finish. This in-focus condition is related to a distance between…
Intelligent probe card architecture
Granted: December 11, 2007
Patent Number:
7307433
A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or…
Lithographic contact elements
Granted: October 30, 2007
Patent Number:
7287322
A method of forming an interconnection, including a spring contact element, by lithographic techniques. In one embodiment, the method includes applying a masking material over a first portion of a substrate, the masking material having an opening which will define a first portion of a spring structure, depositing a structure material (e.g., conductive material) in the opening, and overfilling the opening with the structure material, removing a portion of the structure material, and…
Apparatus and method for managing thermally induced motion of a probe card assembly
Granted: October 23, 2007
Patent Number:
7285968
A probe card assembly can include a probe head assembly having probes for contacting an electronic device to be tested. The probe head assembly can be electrically connected to a wiring substrate and mechanically attached to a stiffener plate. The wiring substrate can provide electrical connections to a testing apparatus, and the stiffener plate can provide structure for attaching the probe card assembly to the testing apparatus. The stiffener plate can have a greater mechanical strength…
Probe head arrays
Granted: October 16, 2007
Patent Number:
7282933
A probe head for testing devices formed on a semiconductor wafer includes a plurality of probe DUT (device under test) arrays. Each device under test includes pads that are urged into pressure contact with probes in a corresponding probe DUT array. The probe arrays patterns have discontinuities such as indentations, protuberances, islands and openings that are opposite at least one device when the probes contact the pads.
Closed-grid bus architecture for wafer interconnect structure
Granted: October 2, 2007
Patent Number:
7276922
An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first…
Apparatuses and methods for planarizing a semiconductor contactor
Granted: August 28, 2007
Patent Number:
7262611
A wiring substrate can include a substrate material, which can have a first surface and a second surface. A plurality of first electrically conductive elements can be disposed on the first surface, and a plurality of second electrically conductive elements can be disposed on the second surface. Ones of the first conductive elements can be electrically connected through the substrate material to ones of the second conductive elements. A mechanism can be located in a first region, which…
Bi-directional buffer for interfacing test system channel
Granted: August 28, 2007
Patent Number:
7262624
An emitter follower or source follower transistor is provided in the channel of a wafer test system between a DUT and a test system controller to enable a low power DUT to drive a test system channel. A bypass resistor is included between the base and emitter of the emitter follower transistor to enable bi-directional signals to be provided between the DUT channel and test system controller, as well as to enable parametric tests to be performed. The emitter follower transistor and bypass…
