Method for making a socket to perform testing on integrated circuits
Granted: July 26, 2005
Patent Number:
6920689
A interconnect structure is inexpensively manufactured and easily insertable into a socket. The interconnect structure is manufactured by forming a sacrificial substrate with cavities that is covered by a masking material having openings corresponding to the cavities. A first plating process is performed by depositing conductive material, followed by coupling wires within the openings and performing another plating process by depositing more conductive material. The interconnect…
Integrated circuit tester with high bandwidth probe assembly
Granted: July 12, 2005
Patent Number:
6917210
Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.
Methods of removably mounting electronic components to a circuit board, and sockets formed by the methods
Granted: July 5, 2005
Patent Number:
6913468
Surface-mount, solder-down sockets are described which permit electronic components such as semiconductor packages to be releasably mounted to a circuit board. Generally, the socket includes resilient contact structures extending from a top surface of a support substrate, and solder-ball (or other suitable) contact structures disposed on a bottom surface of the support substrate. Composite interconnection elements are described for use as the resilient contact structures disposed atop…
Method for fabricating an IC interconnect system including an in-street integrated circuit wafer via
Granted: June 28, 2005
Patent Number:
6910268
Vertical holes are created in streets separating individual integrated circuit (IC) dies formed on a semiconductor wafer, the holes spanning saw-lines along which the wafer is to be later cut to separate the IC die from one another to form individual IC chips. The holes are then filled with conductive material. After the wafer is cut along the saw-lines, portions of the conductive material on opposing sides of the saw-lines remain on peripheral edges of the IC chip to form signal paths…
Apparatus and method for electromechanical testing and validation of probe cards
Granted: June 28, 2005
Patent Number:
6911814
A method of testing a probe card includes the step of positioning the probe card in a prober over a verification wafer that is placed on a stage. The probe card is brought in contact with a contact region on the verification wafer. The verification wafer includes a shorting plane surrounding the contact region. A test signal is sent through the verification wafer to the probe card. A response signal from the probe card is received and analyzed.
High performance probe system
Granted: June 28, 2005
Patent Number:
6911835
A probe system for providing signal paths between an integrated circuit (IC) tester and input/output, power and ground pads on the surfaces of ICs to be tested includes a probe board assembly, a flex cable and a set of probes arranged to contact the IC's I/O pads. The probe board assembly includes one or more rigid substrate layers with traces and vias formed on or within the substrate layers providing relatively low bandwidth signal paths linking the tester to probes accessing some of…
Probe card cooling assembly with direct cooling of active electronic components
Granted: May 10, 2005
Patent Number:
6891385
A probe card cooling assembly for use in a test system includes a package with one or more dies cooled by direct cooling. The cooled package includes one or more dies with active electronic components and at least one coolant port that allows a coolant to enter the high-density package and directly cool the active electronic components of the dies during a testing operation.
Method for processing an integrated circuit including placing dice into a carrier and testing
Granted: May 3, 2005
Patent Number:
6887723
Methods for processing at least one die which comprises an integrated circuit. In one example of a method of the invention, an identification code is applied to a carrier. A singulated die is deposited into the carrier which holds the singulated die. The singulated die comprises an integrated circuit. The identification code may be applied to the carrier before or after depositing the singulated die into the carrier. The carrier may be used in testing the singulated die and may include a…
Test head assembly for electronic components with plurality of contoured microelectronic spring contacts
Granted: May 3, 2005
Patent Number:
6888362
An electronic component is disclosed, having a plurality of microelectronic spring contacts mounted to a planar face of the component. Each of the microelectronic spring contacts has a contoured beam, which may be formed of an integral layer of resilient material deposited over a contoured sacrificial substrate, and comprises a base mounted to the planar face of the component, a beam connected to the base at a first end of the beam, and a tip positioned at a free end of the beam opposite…
Multiple die interconnect system
Granted: April 19, 2005
Patent Number:
6882546
A multiple integrated circuit (IC) die assembly includes a base IC die and secondary IC dice mounted on a surface of the base IC die. A set of protruding contacts formed on the surface of the base IC die and extending beyond the secondary IC dice link the surface of the base IC die to a printed circuit board (PCB) substrate with the secondary IC die residing between the base IC die and the PCB substrate.
Electromagnetically coupled interconnect system
Granted: April 19, 2005
Patent Number:
6882239
An electromagnetic interconnect method and apparatus effects contactless, proximity connections between elements in an electronics system. Data to be communicated between elements in an electronic system are modulated into a carrier signal and transmitted contactlessly by electromagnetic coupling. The electromagnetic coupling may be directly between elements in the system or through an intermediary transmission medium.
Insulative covering of probe tips
Granted: March 22, 2005
Patent Number:
6870381
An insulative material is applied to one or more selected probe tips to disable those probes, and the probes are brought into contact with a semiconductor die. One or more tests are run on the die to verify sufficient testing of the die without the disabled probes. The process may be repeated with other probes disabled to determine which probes need not be used in testing the die.
Method of manufacturing a probe card
Granted: March 8, 2005
Patent Number:
6864105
A method of designing and manufacturing a probe card assembly includes prefabricating one or more elements of the probe card assembly to one or more predefined designs. Thereafter, design data regarding a newly designed semiconductor device is received along with data describing the tester and testing algorithms to be used to test the semiconductor device. Using the received data, one or more of the prefabricated elements is selected. Again using the received data, one or more of the…
Process and apparatus for adjusting traces
Granted: March 1, 2005
Patent Number:
6862727
Traces routed through a computer depiction of a routing area of a system, such as an electronics system, comprise a plurality of connected nodes. The traces may be smoothed, straightened, or otherwise adjusted (e.g., to correct design rule violations) by assigning forces to the nodes and moving the nodes in accordance with the nodes. The forces may be based on such things as the proximity of the nodes to each other and to obstacles in the routing area.
Probe card with coplanar daughter card
Granted: February 15, 2005
Patent Number:
6856150
A probe card assembly includes a printed circuit board with tester contacts for making electrical connections to a semiconductor tester. The probe card assembly also includes a probe head assembly with probes for contacting a semiconductor device under test. One or more daughter cards is mounted to the printed circuit board such that they are substantially coplanar with the printed circuit board. The daughter cards may contain a circuit for processing test data, including test signals to…
Method of designing, fabricating, testing and interconnecting an IC to external circuit nodes
Granted: January 18, 2005
Patent Number:
6845491
A method for designing integrated circuits (ICs) and their interconnect systems includes IC component cells and interconnect component cells in a cell library. Each IC component cell provides both a physical and behavioral model of a component that may be incorporated into the IC while each interconnect component cell includes both a physical and behavioral model of a separate internal or external component of an interconnect system that may link the IC to external nodes. Both the IC and…
Method for manufacturing a multi-layer printed circuit board
Granted: January 11, 2005
Patent Number:
6839964
A method of manufacturing a multilayer printed circuit board (PCB) is provided, the PCB having blind vias connecting to power layers. A portion of the blind vias in the power layers are grouped together to form a cluster of blind vias. Signal layers, provided separate from the power layers, include signal routing channels, with at least some of the signal routing channels aligned above or below the cluster of blind vias of the power layers.
Method and apparatus for shaping spring elements
Granted: January 4, 2005
Patent Number:
6836962
Interconnection elements for electronic components, exhibiting desirable mechanical characteristic (such as resiliency, for making pressure contacts) are formed by using a shaping tool (512) to shape an elongate core element (502) of a soft material (such as gold or soft copper wire) to have a springable shape (including cantilever beam, S-shape, U-shape), and overcoating the shaped core element with a hard material (such as nickel and its alloys), to impart to desired spring (resilient)…
Probe card assembly
Granted: January 4, 2005
Patent Number:
6838893
In a probe card assembly, a series of probe elements can be arrayed on a silicon space transformer. The silicon space transformer can be fabricated with an array of primary contacts in a very tight pitch, comparable to the pitch of a semiconductor device. One preferred primary contact is a resilient spring contact. Conductive elements in the space transformer are routed to second contacts at a more relaxed pitch. In one preferred embodiment, the second contacts are suitable for directly…
ELECTRICAL CONTACT STRUCTURES FORMED BY CONFIGURING A FLEXIBLE WIRE TO HAVE A SPRINGABLE SHAPE AND OVERCOATING THE WIRE WITH AT LEAST ONE LAYER OF A RESILIENT CONDUCTIVE MATERIAL, METHODS OF MOUNTING THE CONTACT STRUCTURES TO ELECTRONIC COMPONENTS, AND APPLICATIONS FOR EMPLOYING THE CONTACT STRUCTURES
Granted: December 28, 2004
Patent Number:
6835898
Contact structures exhibiting resilience or compliance for a variety of electronic components are formed by bonding a free end of a wire to a substrate, configuring the wire into a wire stem having a springable shape, severing the wire stem, and overcoating the wire stem with at least one layer of a material chosen primarily for its structural (resiliency, compliance) characteristics.
