High frequency printed circuit board via
Granted: December 9, 2003
Patent Number:
6661316
A printed circuit board (PCB) via, providing a conductor extending vertically between microstrip or stripline conductors formed on separate layers of a PCB, includes a conductive pad surrounding the conductor and embedded within the PCB between those PCB layers. The pad's shunt capacitance and the magnitudes of capacitances of other portions of the via are sized relative to the conductor's inherent inductance to optimize frequency response characteristics of the via.
Method and apparatus for burning-in semiconductor devices in wafer form
Granted: December 2, 2003
Patent Number:
6655023
Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same…
Predictive, adaptive power supply for an integrated circuit under test
Granted: December 2, 2003
Patent Number:
6657455
A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the…
Method and apparatus for the transport and tracking of an electronic component
Granted: November 11, 2003
Patent Number:
6644982
An apparatus for use in manipulating one or more IC die through testing after they have been cut from the original wafer. A carrier supports the die during the transport, testing, and/or final application. The die is placed into the carrier through an opening and then resides on a ledge lining some portion of the base of the opening. The spring components of the die extend downward through the opening and past the lower side of the ledge to allow for electrical contact. The die may be…
Integrated circuit interconnect system
Granted: November 11, 2003
Patent Number:
6646520
In an interconnect system for providing access to a common I/O terminal for multiple circuit devices such as drivers, receivers and electrostatic discharge (ESD) protection devices implemented on an IC, each such device is provided with a separate contact pad within the IC. The contact pads are linked to one another and to the IC I/O terminal though inductive conductors such as bond wires, metalization layer traces in the IC, or legs of a forked, lithographically-defined spring contact…
Segmented contactor
Granted: November 4, 2003
Patent Number:
6640415
A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into…
Method of fabricating shaped springs
Granted: November 4, 2003
Patent Number:
6640432
A method of fabricating and using an interconnection element that includes a first element material adapted to be coupled to a substrate and a second element material comprising a material having a transformable property such that upon transformation, a shape of the interconnection is deformed. An example is a material that has a transformable property such that a volume of the first and/or second element material may undergo a thermal transformation from one volume to a different volume…
Sockets for “springed” semiconductor devices
Granted: November 4, 2003
Patent Number:
6642625
Temporary connections to spring contact elements extending from an electronic component such as a semiconductor device are made by urging the electronic component, consequently the ends of the spring contact elements, vertically against terminals of an interconnection substrate, or by horizontally urging terminals of an interconnection substrate against end portions of the spring contact elements. A variety of terminal configurations are disclosed.
Method for mounting an electronic component
Granted: September 30, 2003
Patent Number:
6627483
A method for mounting an electronic component. In one example of this method, the electronic component is an integrated circuit which is placed against an element of a carrier, such as a frame of a carrier. The electronic component has a plurality of elongate, resilient, electrical contact elements which are mounted on a corresponding first electrical contact pads on the electronic component. The electronic component is secured to the carrier, aNd the carrier is pressed against a first…
Stacked semiconductor device assembly with microelectronic spring contacts
Granted: September 30, 2003
Patent Number:
6627980
A three-dimensional, stacked semiconductor device assembly with microelectronic spring contacts, and components thereof, is disclosed. The assembly comprises a plurality of stacked modules, which are capable of being readily mounted to, and demounted from, one another. Each module of the assembly comprises a semiconductor device, comprising a die, mounted to an stacking substrate. The die and the stacking substrate are optionally capable of being readily mounted to, and demounted from…
Probe card assembly
Granted: September 23, 2003
Patent Number:
6624648
A probe card assembly includes a probe card, a space transformer, and an interposer disposed between the space transformer and the probe card. Suitable mechanisms for adjusting the orientation of the space transformer without changing the orientation of the probe card, and for determining what adjustments to make, are disclosed.
Special contact points for accessing internal circuitry of an integrated circuit
Granted: September 16, 2003
Patent Number:
6621260
One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits…
System for calibrating timing of an integrated circuit wafer tester
Granted: September 16, 2003
Patent Number:
6622103
A timing calibration system for a wafer level integrated circuit (IC) tester is disclosed. The tester includes channels linked by paths through an interconnect system to pads of the IC. During a test each channel may send a test signal edge to an IC pad following a clock signal edge with a delay including “programmable drive” delay and “drive calibration” delay components, or may sample an IC output signal following the clock signal edge with a delay including…
Probe card assembly and kit, and methods of making same
Granted: September 9, 2003
Patent Number:
6615485
A probe card assembly includes a probe card, a space transformer having resilient contact structures (probe elements) mounted directly to (i.e., without the need for additional connecting wires or the like) and extending from terminals on a surface thereof, and an interposer disposed between the space transformer and the probe card. The space transformer and interposer are “stacked up” so that the orientation of the space transformer, hence the orientation of the tips of the…
Method of making lithographic contact springs
Granted: September 9, 2003
Patent Number:
6616966
A method of forming an interconnection, including a spring contact element, by lithographic techniques. In one embodiment, the method includes applying a masking material over a first portion of a substrate, the masking material having an opening which will define a first portion of a spring structure, depositing a structure material (e.g., conductive material) in the opening, and overfilling the opening with the structure material, removing a portion of the structure material, and…
Filter structures for integrated circuit interfaces
Granted: August 12, 2003
Patent Number:
6606014
An interconnect system for linking integrated circuits (ICs) mounted on a surface of a printed circuit board (PCB) includes a trace positioned below the surface, one or more vias linking the trace to the surface of the PCB, and other conductors linking pads on the ICs to the vias. Impedances of the various components of the interconnect system are sized relative to one another to optimize interconnect system frequency response.
Cross-correlation timing calibration for wafer-level IC tester interconnect systems
Granted: August 12, 2003
Patent Number:
6606575
To calibrate timing of test signals generated by all channels of an integrated circuit, each channel is programmed to generate a test signal having a repetitive pseudo-random test signal edge pattern. The test signal pattern of each channel is compared to a reference signal having the same edge pattern and the delay of each channel is adjusted to maximize cross-correlation between the test signal and the reference signal.
Closed-grid bus architecture for wafer interconnect structure
Granted: August 5, 2003
Patent Number:
6603323
An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first…
Special contact points for accessing internal circuitry of an integrated circuit
Granted: August 5, 2003
Patent Number:
6603324
One embodiment of the present invention concerns an integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits…
Special contact points for accessing internal circuitry of an integrated circuit
Granted: July 22, 2003
Patent Number:
6597187
An integrated circuit that includes bond pads and special contact pads or points. The bond pads are for interfacing the integrated circuit as a whole with an external circuit, and are to be bonded to a package or circuit board. The bond pads are disposed on the die in a predetermined alignment such as a peripheral, grid, or lead-on-center alignment. The special contact pads are used to provide external test patterns to internal circuits and/or to externally monitor results from testing…
