Efficient parallel testing of semiconductor devices using a known good device to generate expected responses
Granted: May 6, 2003
Patent Number:
6559671
A system for testing integrated circuit devices is disclosed in which a tester communicates with a known good device through a channel. Tester-DUT interface circuitry is provided for monitoring the channel while the tester is writing data as part of a test sequence to locations in the known good device. In response, the interface circuitry writes the data to corresponding locations in each of a number of devices under test (DUTs). The interface circuitry monitors the channel while the…
Test assembly including a test die for testing a semiconductor product die
Granted: April 22, 2003
Patent Number:
6551844
One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry…
Method for manufacturing raised electrical contact pattern of controlled geometry
Granted: March 25, 2003
Patent Number:
6538214
An interposer includes a substrate having opposing surfaces. Conductive terminals are disposed on both surfaces, and conductive terminals on one surface are electrically connected to conductive terminals on the opposing surface. Elongate, springable, conducive interconnect elements are fixed to conductive terminals on both surfaces.
High frequency printed circuit board via
Granted: March 25, 2003
Patent Number:
6538538
A printed circuit board (PCB) via, providing a conductor extending vertically between microstrip or stripline conductors formed on separate layers of a PCB, includes a conductive pad surrounding the conductor and embedded within the PCB between those PCB layers. The pad's shunt capacitance and the magnitudes of capacitances of other portions of the via are sized relative to the conductor's inherent inductance to optimize frequency response characteristics of the via.
Method of designing, fabricating, testing and interconnecting an IC to external circuit nodes
Granted: March 25, 2003
Patent Number:
6539531
A method for designing integrated circuits (ICs) and their interconnect systems includes IC component cells and interconnect component cells in a cell library. Each IC component cell provides both a physical and behavioral model of a component that may be incorporated into the IC while each interconnect component cell includes both a physical and behavioral model of a separate internal or external component of an interconnect system that may link the IC to external nodes. Both the IC and…
Sockets for “springed” semiconductor devices
Granted: March 18, 2003
Patent Number:
6534856
Temporary connections to spring contact elements extending from an electronic component such as a semiconductor device are made by urging the electronic component, consequently the ends of the spring contact elements, vertically against terminals of an interconnection substrate, or by horizontally urging terminals of an interconnection substrate against end portions of the spring contact elements. A variety of terminal configurations are disclosed.
Wafer-level burn-in and test
Granted: February 25, 2003
Patent Number:
6525555
Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly…
Microelectronic contact structures, and methods of making same
Granted: February 18, 2003
Patent Number:
6520778
Microelectronic contact structures are fabricated by separately forming, then joining together, various components thereof. Each contact structure has three components: a “post” component, a “beam” component, and a “tip” component. The resulting contact structure, mounted to an electronic component, is useful for making an electrical connection with another electronic component. The post component can be, fabricated on a sacrificial substrate, joined…
Planarizer for a semiconductor contactor
Granted: January 21, 2003
Patent Number:
6509751
A planarizer for a probe card assembly. A planarizer includes a first control member extending from a substrate in a probe card assembly. The first control member extends through at least one substrate in the probe card assembly and is accessible from an exposed side of an exterior substrate in the probe card assembly. Actuating the first control member causes a deflection of the substrate connected to the first control member.
Integrated circuit tester with high bandwidth probe assembly
Granted: December 31, 2002
Patent Number:
6501343
Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.
Distributed interface for parallel testing of multiple devices using a single tester channel
Granted: December 24, 2002
Patent Number:
6499121
A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester and providing error information concerning the DUTs. The interface circuitry forwards data values (received from the tester over a single channel) to a number of DUTs in parallel. The circuitry performs comparisons using data values read from the DUTs, and in response generates error values…
Methods for making spring interconnect structures
Granted: December 10, 2002
Patent Number:
6491968
A method including fabricating a multi-tiered structure to form a compact, resilient interconnect structure. Fabricating each tier or leaf includes, in one aspect, providing a base substrate material, and applying a masking material over the base substrate material. An opening is patterned in the masking material and a resilient element is formed in the opening. A resilient element is coupled to the resilient element to form the resulting product. The method includes repeating this…
Microelectronic spring contact element and electronic component having a plurality of spring contact elements
Granted: November 19, 2002
Patent Number:
6482013
Spring contact elements having a base end portion, a contact end portion, and a central body portion. In a first embodiment, the spring contact elements provide for movement of a majority of the spring contact element characterized by a first spring constant. As the force and deflection increase, the movement of a rearward portion of the spring contact element will stop when a portion of the contact element abuts a portion of its mounting member while the movement of a forward portion…
Probe card for probing wafers with raised contact elements
Granted: November 19, 2002
Patent Number:
6483328
A probe card is provided for contacting an electric componet with raised contact elements. In particular, the present invention is useful for contacting a semiconductor wafer with resilient contact elements, such as springs. A probe card is designed to have terminals to mate with the contact elements on the wafer. In a preferred embodiment, the terminals are posts. In a preferred embodiment the terminals include a contact material suitable for repeated contacts. In one particularly…
Semiconductor fuse covering
Granted: November 12, 2002
Patent Number:
6479308
A method and system for sealing or covering exposed fuses on a semiconductor device are disclosed. A semiconductor device prober incorporating a spray device for applying a sealing compound to individual fuses on a semiconductor device subsequent to testing the semiconductor device is disclosed. A method and system for sealing exposed fuses on a semiconductor device is disclosed which allows the sealing step to be performed either prior to or following singulation of the semiconductor…
Parallel testing of integrated circuit devices using cross-DUT and within-DUT comparisons
Granted: November 12, 2002
Patent Number:
6480978
What is disclosed is a system for testing a plurality of integrated circuit devices under test (DUTs), that includes a tester having at least one set of tester input/output (I/O) lines, the tester providing data values for testing a single DUT on the set of tester I/O lines, and circuitry coupled to the set of tester I/O lines to receive the data values from the tester and to provide error values to the tester, the circuitry forwards the data values to each of the plurality of DUTs, the…
Method of making microelectronic contact structures
Granted: November 5, 2002
Patent Number:
6475822
Spring contact elements are fabricated by depositing at least one layer of metallic material into openings defined on a sacrificial substrate. The openings may be within the surface of the substrate, or in one or more layers deposited on the surface of the sacrificial substrate. Each spring contact element has a base end portion, a contact end portion, and a central body portion. The contact end portion is offset in the z-axis (at a different height) than the central body portion. The…
Raised contact structures (solder columns)
Granted: November 5, 2002
Patent Number:
6476333
An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is…
Method for testing signal paths between an integrated circuit wafer and a wafer tester
Granted: November 5, 2002
Patent Number:
6476630
Signal paths within an interconnect structure linking input/output (I/O) ports of an integrated circuit (IC) tester and test points of an IC die on a wafer are tested for continuity, shorts and resistance by using the interconnect structure to access a similar arrangement of test points on a reference wafer. Conductors in the reference wafer interconnect groups of test points. The tester may then test the continuity of signal paths through the interconnect structure by sending test…
Electrical contactor especially wafer level contactor using fluid pressure
Granted: October 22, 2002
Patent Number:
6468098
An electrical interconnect assembly and methods for making an electrical interconnect assembly. In one embodiment, an interconnect assembly includes a flexible wiring layer having a plurality of first contact elements and a fluid containing structure which is coupled to the flexible wiring layer. The fluid, when contained in the fluid containing structure, presses the flexible wiring layer towards a device under test to form electrical interconnections between the first contact elements…
