Pipeline architecture for bitwise multiplier-accumulator (MAC)
Granted: March 26, 2024
Patent Number:
11941407
A unit for accumulating a plurality N of multiplied M bit values includes a receiving unit, a bit-wise multiplier and a bit-wise accumulator. The receiving unit receives a pipeline of multiplicands A and B such that, at each cycle, a new set of multiplicands is received. The bit-wise multiplier bit-wise multiplies bits of a current multiplicand A with bits of a current multiplicand B and to sum and carry between bit-wise multipliers. The bit-wise accumulator accumulates output of the…
One by one selection of items of a set
Granted: January 2, 2024
Patent Number:
11860885
An associative memory array includes a plurality of associative memory cells arranged in rows and columns where each first cell in a first row and in a first column has access to a content of a second cell in a second row in an adjacent column.
Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
Granted: September 19, 2023
Patent Number:
11763881
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
Neural hashing for similarity search
Granted: September 19, 2023
Patent Number:
11763136
A system for training a neural-network-based floating-point-to-binary feature vector encoder preserves the locality relationships between samples in an input space over to an output space. The system includes a neural network under training and a probability distribution loss function generator. The neural network has floating-point inputs and floating-point pseudo-bipolar outputs. The generator compares an input probability distribution constructed from floating-point cosine…
Concurrent multi-bit adder
Granted: June 20, 2023
Patent Number:
11681497
A method for an associative memory device includes storing a plurality of pairs of N-bit numbers A and B to be added together in columns of a memory array of the associative memory device, each pair in a column, each bit in a row of the column, and dividing each N-bit number A and B into groups containing M bits each, having group carry-out predictions for every group except a first group, the group carry-out predictions calculated for any possible group carry-in value, and, once the…
Memory device for determining an extreme value
Granted: June 6, 2023
Patent Number:
11670369
A method to determine an extreme value of a plurality of data candidates includes storing each data candidate of a plurality of data candidates in a separate column of an associative memory, initializing a row of marker bits by setting each marker bit to a value of 1, computing a subsequent row of marker bits by performing in parallel a Boolean AND operation between a previous row of marker bits and a row of bits of the data candidates, starting with the row of most significant bits of…
Efficient similarity search
Granted: May 9, 2023
Patent Number:
11645292
A system for measuring similarity between a binary query vector and a plurality of binary candidate vectors includes a storage unit and a processor. The storage unit stores the binary query vector and the plurality of candidate vectors, and the processor performs Tanimoto calculations in terms of Hamming distances. The processor includes a Tanimoto to Hamming threshold converter, a Hamming measurer, and a Hamming comparator. The Tanimoto to Hamming threshold converter converts a Tanimoto…
Efficient similarity search
Granted: May 9, 2023
Patent Number:
11645292
A system for measuring similarity between a binary query vector and a plurality of binary candidate vectors includes a storage unit and a processor. The storage unit stores the binary query vector and the plurality of candidate vectors, and the processor performs Tanimoto calculations in terms of Hamming distances. The processor includes a Tanimoto to Hamming threshold converter, a Hamming measurer, and a Hamming comparator. The Tanimoto to Hamming threshold converter converts a Tanimoto…
In-memory full adder
Granted: March 14, 2023
Patent Number:
11604850
A non-destructive memory array implements a full adder. The array includes a column connected by a bit line and a full adder unit. The column stores a first bit in a first row of the bit line, a second bit in a second row of the bit line, and an inverse of a carry-in bit in a third row of the bit line. The full adder unit stores, in the second and third rows of the bit line, a sum bit and a carry out bit output, respectively, of adding the first bit, the second bit and the carry-in bit.…
Angle recorder for surgery
Granted: March 7, 2023
Patent Number:
D980423
Angle recorder for surgery
Granted: March 7, 2023
Patent Number:
D980422
In-memory efficient multistep search
Granted: December 6, 2022
Patent Number:
11520791
A system for performing cascading search includes an associative memory array, a controller, a similarity search processor and an exact match processor. The associative memory array stores a plurality of multiportion data vectors stored in at least one column of the associative memory array. Each vector has a first portion and a second portion which are aligned to each other in the column. The controller controls the associative memory array to perform a similarity search of a similarity…
Write data processing methods associated with computational memory cells
Granted: February 22, 2022
Patent Number:
11257540
A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.
Storage array circuits and methods for computational memory cells
Granted: January 18, 2022
Patent Number:
11227653
A storage array for computational memory cells formed as a memory/processing array provides storage of the data without using the more complicated computational memory cells for storage. The storage array may have multiple columns of the storage cells coupled to a column of the computational memory cells. The storage array may have ECC circuitry.
Read data processing circuits and methods associated with computational memory cells
Granted: December 21, 2021
Patent Number:
11205476
A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells…
Processing array device that performs one cycle full adder operation and bit line read/write logic features
Granted: December 7, 2021
Patent Number:
11194548
A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.
Results processing circuits and methods associated with computational memory cells
Granted: December 7, 2021
Patent Number:
11194519
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
Computational memory cell and processing array device using memory cells
Granted: October 19, 2021
Patent Number:
11150903
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.
Write data processing circuits and methods associated with computational memory cells
Granted: August 17, 2021
Patent Number:
11094374
A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.
Responder signal circuitry for memory arrays finding at least one cell with a predefined value
Granted: July 27, 2021
Patent Number:
11074973
A memory device includes a memory array of non-volatile memory cells arranged in rows and columns and responder signal circuitry. The responder signal circuitry performs a calculation on a row of the memory array and generates a responder signal indicating that there is at least one cell in the row having a predefined value.
