Efficient similarity search
Granted: May 9, 2023
Patent Number:
11645292
A system for measuring similarity between a binary query vector and a plurality of binary candidate vectors includes a storage unit and a processor. The storage unit stores the binary query vector and the plurality of candidate vectors, and the processor performs Tanimoto calculations in terms of Hamming distances. The processor includes a Tanimoto to Hamming threshold converter, a Hamming measurer, and a Hamming comparator. The Tanimoto to Hamming threshold converter converts a Tanimoto…
In-memory full adder
Granted: March 14, 2023
Patent Number:
11604850
A non-destructive memory array implements a full adder. The array includes a column connected by a bit line and a full adder unit. The column stores a first bit in a first row of the bit line, a second bit in a second row of the bit line, and an inverse of a carry-in bit in a third row of the bit line. The full adder unit stores, in the second and third rows of the bit line, a sum bit and a carry out bit output, respectively, of adding the first bit, the second bit and the carry-in bit.…
Angle recorder for surgery
Granted: March 7, 2023
Patent Number:
D980423
Angle recorder for surgery
Granted: March 7, 2023
Patent Number:
D980422
In-memory efficient multistep search
Granted: December 6, 2022
Patent Number:
11520791
A system for performing cascading search includes an associative memory array, a controller, a similarity search processor and an exact match processor. The associative memory array stores a plurality of multiportion data vectors stored in at least one column of the associative memory array. Each vector has a first portion and a second portion which are aligned to each other in the column. The controller controls the associative memory array to perform a similarity search of a similarity…
Write data processing methods associated with computational memory cells
Granted: February 22, 2022
Patent Number:
11257540
A write data processing method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array.
Storage array circuits and methods for computational memory cells
Granted: January 18, 2022
Patent Number:
11227653
A storage array for computational memory cells formed as a memory/processing array provides storage of the data without using the more complicated computational memory cells for storage. The storage array may have multiple columns of the storage cells coupled to a column of the computational memory cells. The storage array may have ECC circuitry.
Read data processing circuits and methods associated with computational memory cells
Granted: December 21, 2021
Patent Number:
11205476
A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells…
Results processing circuits and methods associated with computational memory cells
Granted: December 7, 2021
Patent Number:
11194519
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
Processing array device that performs one cycle full adder operation and bit line read/write logic features
Granted: December 7, 2021
Patent Number:
11194548
A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.
Computational memory cell and processing array device using memory cells
Granted: October 19, 2021
Patent Number:
11150903
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.
Write data processing circuits and methods associated with computational memory cells
Granted: August 17, 2021
Patent Number:
11094374
A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.
Responder signal circuitry for memory arrays finding at least one cell with a predefined value
Granted: July 27, 2021
Patent Number:
11074973
A memory device includes a memory array of non-volatile memory cells arranged in rows and columns and responder signal circuitry. The responder signal circuitry performs a calculation on a row of the memory array and generates a responder signal indicating that there is at least one cell in the row having a predefined value.
Computational memory cell and processing array device using the memory cells for XOR and XNOR computations
Granted: May 4, 2021
Patent Number:
10998040
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
In memory matrix multiplication and its usage in neural networks
Granted: May 4, 2021
Patent Number:
10997275
A method for an associative memory array includes storing each column of a matrix in an associated column of the associative memory array, where each bit in row j of the matrix is stored in row R-matrix-row-j of the array, storing a vector in each associated column, where a bit j from the vector is stored in an R-vector-bit-j row of the array. The method includes simultaneously activating a vector-matrix pair of rows R-vector-bit-j and R-matrix-row-j to concurrently receive a result of a…
Computational memory cell and processing array device using complementary exclusive or memory cells
Granted: March 23, 2021
Patent Number:
10958272
A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
One by one selection of items of a set
Granted: March 23, 2021
Patent Number:
10956432
A method and a system for selecting items one by one from a set of items in an associative memory array includes determining a density of the set, if the density is sparse, repeatedly performing an extreme item select (EIS) method to select a next one of the elected items from the set and removing the next one from the set to create a next set, and if the density is not sparse, performing a next index select (NIS) method to create a linked list of the elected items and to repeatedly…
Precise exponent and exact softmax computation
Granted: March 16, 2021
Patent Number:
10949766
A method for an associative memory device includes dividing a multi-bit mantissa A of a number X to a plurality of smaller partial mantissas Aj, offline calculating a plurality of partial exponents F(Aj) for each possible value of each partial mantissa Aj and storing the plurality of partial exponents F(Aj) in a look up table (LUT) of the associative memory device. A system includes an associative memory array to store a plurality of partial mantissas Ai of a mantissa A of a number X and…
Method for min-max computation in associative memory
Granted: March 9, 2021
Patent Number:
10942736
A method for finding an extreme value among a plurality of numbers in an associative memory includes creating a spread-out representation (SOR) for each number of the plurality of numbers, storing each SOR in a column of the associative memory array and performing a horizontal bit-wise Boolean operation on rows of the associative memory array to produce an extreme SOR (ESOR) having the extreme value. A system for finding an extreme value includes an associative memory array to store the…
Ultra low VDD memory cell with ratioless write port
Granted: March 9, 2021
Patent Number:
10943648
An ultra low VDD memory cell has a ratioless write port. In some embodiments, the VDD operation level can be as low as the threshold voltage of NMOS and PMOS transistors of the cell.
