Processing array device that performs one cycle full adder operation and bit line read/write logic features
Granted: February 23, 2021
Patent Number:
10930341
A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.
Finding K extreme values in constant processing time
Granted: February 23, 2021
Patent Number:
10929751
A method includes determining a set of k extreme values of a dataset of elements in a constant time irrespective of the size of the dataset. A method creates a set of k indicators, each indicator associated with one multi-bit binary number in a large dataset of multi-bit binary numbers. The method includes arranging the multi-bit binary numbers such that each bit n of each said multi-bit binary number is located in a different row n of an associative memory array, starting from a row…
Error detecting memory device
Granted: February 16, 2021
Patent Number:
10922169
A memory device includes a non-destructive memory array that includes memory cells arranged in rows and columns. The array includes a plurality of word lines, first bit lines and second bit lines, a NOR gate per column Each word line activates memory cells in a row and thereby establishes an activated row. First bit lines and second bit lines connect memory cells in columns, each first bit line provides the result of a Boolean AND operation between data stored in the first activated row…
Massively parallel, associative multiplier accumulator
Granted: January 12, 2021
Patent Number:
10891991
An in-memory multiplier-accumulator includes a memory array, a multi-bit multiplier and a multi-bit layered adder. The memory array has a multiplicity of rows and columns, each column being divided into a plurality of bit line processors and each bit line processor operating on its associated pair of input values. The multi-bit multiplier utilizes each bit line processor to multiply the associated pair of input values in each bit line processor to generate multiplication results. The…
Results processing circuits and methods associated with computational memory cells
Granted: January 12, 2021
Patent Number:
10891076
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
Processing array device that performs one cycle full adder operation and bit line read/write logic features
Granted: December 29, 2020
Patent Number:
10877731
A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.
Orthogonal data transposition system and method during data transfers to/from a processing array
Granted: December 8, 2020
Patent Number:
10860320
A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory. Thus, when data words are transferred between storage memory and the processing array, a mechanism orthogonally transposes the data words.
Computational memory cell and processing array device using memory cells
Granted: December 8, 2020
Patent Number:
10860318
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.
Computational memory cell and processing array device with ratioless write port
Granted: December 1, 2020
Patent Number:
10854284
A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.
Write data processing circuits and methods associated with computational memory cells
Granted: November 24, 2020
Patent Number:
10847213
A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.
Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers
Granted: November 24, 2020
Patent Number:
10847212
A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability for selected write data in a bit line section to be logically combined (e.g. logically ANDed) with the read result on a read bit line, as if the write data were the read data output of another computational memory cell being read during the read operation. When accumulation logic is implemented in the bit line sections, the…
Sparse matrix multiplication in associative memory device
Granted: November 24, 2020
Patent Number:
10846365
A method for use in an associative memory device when multiplying by a sparse matrix includes storing only non-zero elements of the sparse matrix in the associative memory device as multiplicands. The storing includes locating the non-zero elements in computation columns of the associative memory device according to linear algebra rules along with their associated multiplicands such that a multiplicand and a multiplier of each multiplication operation to be performed are stored in a same…
Non-volatile in-memory computing device
Granted: November 10, 2020
Patent Number:
10832746
Disclosed is an in-memory computing device including a memory array with non-volatile memory cells arranged in rows and columns; a multiple row decoder to activate at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and circuitry to write data associated with the parametric change into the memory array. Additionally disclosed is a method of computing inside a memory array including…
Concurrent multi-bit adder
Granted: November 3, 2020
Patent Number:
10824394
A system includes an associative memory array and a concurrent adder. The memory array includes a plurality of sections, where each section includes cells arranged in rows and columns. The memory array stores bit j from a first multi-bit number and bit j from a second multi-bit number in a same column in section j. The concurrent adder performs, in parallel, multi-bit add operations of P pairs of multi-bit operands stored in columns of a memory array. Each pair of the P pairs is stored…
Self correcting memory device
Granted: October 27, 2020
Patent Number:
10817370
A self-correcting memory device (SCMD) includes a non-destructive memory array that includes memory cells arranged in rows and columns that includes a storage section, a comparison section, a comparing element, a selective write unit and a row decoder. The storage section stores a first copy, a second copy and a third copy of a data item in physically separated columns. The comparison section temporarily stores the first copy in a first row and the second copy in a second row. The…
Computational memory cell and processing array device using memory cells
Granted: October 27, 2020
Patent Number:
10817292
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.
In-memory stochastic rounder
Granted: October 13, 2020
Patent Number:
10803141
An associative processor includes a memory array and a controller. The memory array stores a multiplicity of N bit stochastic numbers in separate rows of a stochastic section of the memory array and each stochastic number has a same probability distribution P. The controller includes a probability calculator which receives a desired probability distribution Pdesired, determines a Boolean function of a set of the N bit stochastic numbers which produces the probability distribution…
Read data processing circuits and methods associated memory cells
Granted: September 15, 2020
Patent Number:
10777262
A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells…
Computational memory cell and processing array device using memory cells
Granted: July 28, 2020
Patent Number:
10725777
A memory cell that may be used for computation and processing array using the memory cell are capable to performing a logic operation including a boolean AND, a boolean OR, a boolean NAND or a boolean NOR. The memory cell may have a read port that has isolation circuits that isolate the data stored in the storage cell of the memory cell from the read bit line.
Systems and methods involving multi-bank, dual-pipe memory circuitry
Granted: July 21, 2020
Patent Number:
10720205
Multi-bank, dual-pipe SRAM systems, methods, processes of operating such SRAMs, and/or methods of fabricating multi-bank, dual-pipe SRAM are disclosed. For example, one illustrative multi-bank, dual-pipe SRAM may comprise features for capturing read and write addresses, splitting and/or combining them via one or more splitting/combining processes, and/or bussing them to the SRAM memory banks, where they may be read and written to a particular bank. Illustrative multi-bank, dual-pipe…
