Systems and methods involving data bus inversion memory circuitry, configuration and/or operation
Granted: July 5, 2016
Patent Number:
9385032
Systems, methods and fabrication processes relating to memory devices involving data bus inversion are disclosed. According to one illustrative implementation, a memory device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, and circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides…
Systems and methods involving data bus inversion memory circuitry, configuration and/or operation including data signals grouped into 10 bits and/or other features
Granted: July 5, 2016
Patent Number:
9384822
Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI…
Systems and methods involving phase detection with adaptive locking/detection features
Granted: May 31, 2016
Patent Number:
9356611
Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.
Memory systems and methods involving high speed local address circuitry
Granted: April 19, 2016
Patent Number:
9318174
Systems and methods of memory and memory operation are disclosed, such as providing a circuit including a local address driver voltage source for memory decoding. In one exemplary implementation, an illustrative circuit may comprise a first buffer and a capacitor. The first buffer may comprise a power input and a ground input. The capacitor may comprise a first terminal connected to the power input of the first buffer and a second terminal connected to the ground input of the first…
Systems and methods of semiconductor memory devices including features of output buffer initialization circuit(s) and/or multiple power-up detection/handling
Granted: April 12, 2016
Patent Number:
9311971
Systems and methods are disclosed involving adaptive power up features for high-speed synchronous RAM. In one exemplary implementation, there is provided a semiconductor device including a memory cell, power circuitry, and an output buffer with level shifting circuitry. Moreover, the device may include power circuitry comprised of a first power up circuit and a second power up circuit and/or level shifting circuitry comprised of a pull up level shift circuit and a pull down level shift…
Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode
Granted: January 19, 2016
Patent Number:
9240229
Implementations herein involve control I/O buffer enable circuitry and/or features of saving power in standby mode. In illustrative embodiments, aspects of the present innovations may be directed to providing low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.
Systems and methods involving multi-bank, dual- or multi-pipe SRAMs
Granted: November 24, 2015
Patent Number:
9196324
Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide…
Systems and methods of double/quad data rate memory involving input latching, self-timing and/or other features
Granted: October 13, 2015
Patent Number:
9159391
Systems and methods relating to memory and/or memory latching are disclosed. In one exemplary implementation, an illustrative memory device may include self-timed pulse generator circuitry, first input latch circuitry, read/write control circuitry, and second input latch circuitry. According to further implementations herein, fast address access for read and write may be provided in the same cycle via a self-timed pulse in the input latch circuit and/or via associated control/scheme from…
Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features
Granted: September 15, 2015
Patent Number:
9135986
A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described, including embodiments having sectioned bit lines with hierarchical aspects. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. Further, in…
Systems and methods of phase frequency detection involving features such as improved clock edge handling circuitry/aspects
Granted: July 28, 2015
Patent Number:
9094025
Systems and methods herein may include or involve control circuitry that detects missing edges of reference and/or feedback clocks and may block the next N rising edges of the feedback clock or reference clock, respectively. In some implementations, a phase frequency detector (PFD) circuit comprises first circuitry including an output that outputs a missing edge signal. The first circuitry may include components arranged to detect a missing rising edge of one or both of a reference clock…
Systems and methods of phase-locked loop involving closed-loop, continuous frequency range, auto calibration and/or other features
Granted: July 14, 2015
Patent Number:
9083356
Systems and methods involving phase-locked-loop (PLL) circuitry are disclosed. In one illustrative implementation, a PLL circuit device may comprise voltage controlled oscillator (VCO) circuitry having a bias signal that sets a frequency range, circuitry that shifts the VCO circuitry to operate in one of the frequency ranges, and other circuitry to compare/calibrate signals and/or set the bias current. According to further implementations, as a function of operation of the circuitry, an…
Systems and methods of pipelined output latching involving synchronous memory arrays
Granted: June 9, 2015
Patent Number:
9053768
Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the…
Systems and methods involving phase detection with adaptive locking/detection features
Granted: April 28, 2015
Patent Number:
9018992
Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.
Systems and methods involving multi-bank, dual- or multi-pipe SRAMs
Granted: March 17, 2015
Patent Number:
8982649
Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide…
Systems and methods including clock features such as minimization of simultaneous switching outputs (SSO) effects involving echo clocks
Granted: November 11, 2014
Patent Number:
8885439
Systems and methods are disclosed relating to semiconductor memory devices. According to some exemplary implementations, there are provided innovations associated with power and ground pads in devices such as static random access memory (“SRAM”) devices and dynamic random access memory (“DRAM”) devices. Moreover, the systems and/or methods may include features such as minimization of simultaneous switching outputs (SSO) effects relating to echo clock circuitry.
Systems and methods of semiconductor memory devices including features of output buffer initialization circuit(s) and/or multiple power-up detection/handling
Granted: August 26, 2014
Patent Number:
8817550
Systems and methods are disclosed involving adaptive power up features for high-speed synchronous RAM. In one exemplary implementation, there is provided a semiconductor device including a memory cell, power circuitry, and an output buffer with level shifting circuitry. Moreover, the device may include power circuitry comprised of a first power up circuit and a second power up circuit and/or level shifting circuitry comprised of a pull up level shift circuit and a pull down level shift…
Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features
Granted: April 8, 2014
Patent Number:
8693236
A hierarchical sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line in hierarchy, and associated systems and methods are described. In one illustrative implementation, each sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line, and wherein the sectioned bit lines are arranged in…
Systems and methods involving phase detection with adaptive locking/detection features
Granted: January 28, 2014
Patent Number:
8638144
Systems and methods associated with control of clock signals are disclosed. In one exemplary implementation, there is provided a delay-lock-loop (DLL) and/or a delay/phase detection circuit. Moreover, such circuit may comprise digital phase detection circuitry, digital delay control circuitry, analog phase detection circuitry, and analog delay control circuitry. Implementations may include configurations that prevent transition back to the unlocked state due to jitter or noise.
Systems and methods of sectioned bit line memory arrays
Granted: November 26, 2013
Patent Number:
8593860
A sectioned bit line of an SRAM memory device, an SRAM memory device having a sectioned bit line, and associated systems and methods are described. In one illustrative implementation, the sectioned bit line may comprise a local bit line, a memory cell connected to the local bit line, and a pass gate coupled to the local bit line, wherein the pass gate is configured to be coupled to a global bit line. In other implementations, an SRAM memory device may be configured involving sectioned…
Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines
Granted: November 5, 2013
Patent Number:
8575982
The present disclosure relates to systems and methods of noise reduction and/or power saving. According to one or more illustrative implementations, for example, innovations consistent with delay lines in clock/timing circuits such as Delay-Lock-Loop (DLL) and/or Duty Cycle Correction (DCC) circuits are disclosed.
