Systems and methods including clock features such as minimization of simultaneous switching outputs (SSO) effects involving echo clocks
Granted: July 16, 2013
Patent Number:
8488408
Systems and methods are disclosed relating to semiconductor memory devices. According to some exemplary implementations, there are provided innovations associated with power and ground pads in devices such as static random access memory (“SRAM”) devices and dynamic random access memory (“DRAM”) devices. Moreover, the systems and/or methods may include features such as minimization of simultaneous switching outputs (SSO) effects relating to echo clock circuitry.
Systems and methods including features of power supply noise reduction and/or power-saving for high speed delay lines
Granted: March 19, 2013
Patent Number:
8400200
The present disclosure relates to systems and methods of noise reduction and/or power saving. According to one or more illustrative implementations, for example, innovations consistent with delay lines in clock/timing circuits such as Delay-Lock-Loop (DLL) and/or Duty Cycle Correction (DCC) circuits are disclosed.
System and method for refreshing a DRAM device
Granted: February 14, 2012
Patent Number:
8116161
The present invention provides a system and method for refreshing a DRAM device without interrupting or inhibiting read and write operations of the DRAM device. The system may includes refresh control circuitry that selectively generates requests to perform refresh operations and a refresh address counter that is coupled to the refresh control circuitry and that generates a refresh address in response to receiving a refresh request. The refresh address corresponds to a word line of the…
System and method for refreshing a DRAM device
Granted: November 6, 2007
Patent Number:
7292490
The present invention provides a system and method for refreshing a DRAM device without interrupting or inhibiting read and write operations of the DRAM device. The system may includes refresh control circuitry that selectively generates requests to perform refresh operations and a refresh address counter that is coupled to the refresh control circuitry and that generates a refresh address in response to receiving a refresh request. The refresh address corresponds to a word line of the…
Semiconductor memory device with reduced soft error rate (SER) and method for fabricating same
Granted: June 12, 2007
Patent Number:
7230303
The present invention provides a semiconductor memory device with reduced soft error rate (SER) and a method for fabricating such a device. The semiconductor memory device includes a plurality of implants of impurity ions that provide for a reduced number of minority carriers having less mobility. A fabrication process for the semiconductor memory includes a “non-retrograde” implant of impurity ions that is effective to suppress the mobility and lifetime of minority carriers in the…
