FREQUENCY DOMAIN COMPRESSION IN A BASE TRANSCEIVER SYSTEM
Granted: July 12, 2012
Application Number:
20120176966
A method and apparatus provide signal compression for transfer over serial data links in a base transceiver system (BTS) of a wireless communication network. For the uplink, an RF unit of the BTS applies frequency domain compression of baseband signal samples, resulting from analog to digital conversion of received analog signals followed by digital downconversion, forming compressed coefficients. After transfer over the serial data link, the baseband processor then applies frequency…
CONTROLLER FOR SECONDARY SIDE CONTROL OF A SWITCH, POWER CONVERTER, AND RELATED SYNCHRONOUS RECTIFICATION CONTROL METHOD
Granted: July 12, 2012
Application Number:
20120176827
A controller, power converter, and a related method for secondary side control of a switch are disclosed herein. An embodiment of the present invention includes a controller. The controller comprises a drain to source voltage (VDS voltage) input configured to receive the VDS voltage of a transistor, a gate drive output configured to output a gate drive voltage to a gate of the transistor, and control logic configured to initiate a minimum on time signal independent of triggering the gate…
VOLTAGE LEVEL SHIFTING APPARATUSES AND METHODS
Granted: June 14, 2012
Application Number:
20120146688
Level shifting circuits and related methods are disclosed herein. The level shifting circuit includes a cross-coupled pull-up circuit coupled to a higher supply voltage, an output signal, and an inverted output signal. An input signal transitions between a ground and a lower supply voltage and an inverted input signal transitions in a direction opposite from the input signal between the ground and the lower supply voltage. A first n-channel transistor has a gate coupled to the lower…
APPARATUS, SYSTEM, AND METHOD FOR GENERATING A LOW POWER SIGNAL WITH AN OPERATIONAL AMPLIFIER
Granted: May 31, 2012
Application Number:
20120133634
An amplifier, electronic display system, and a related method for generating a low power signal with an operational amplifier are disclosed herein. An embodiment of the present invention includes an amplifier, comprising an operational amplifier and a voltage converter. The operational amplifier includes an inverting input, a non-inverting input, an output, a first power supply input and a second power supply input, and is configured to generate an output signal in response to an input…
FLIP CHIP BUMP ARRAY WITH SUPERIOR SIGNAL PERFORMANCE
Granted: May 3, 2012
Application Number:
20120104596
An integrated circuit (342) that is electrically connected to a printed circuit board (246) with a package substrate (344) includes a circuit body (352), and a bump array (354) that electrically connects the circuit body (352) to the package substrate (244). The bump array (354) includes a first bump set (356) having a plurality of signal bumps (364) and a plurality of non-signal bumps (366) alternatingly interspersed and aligned along an axis. With the present design, the bump array…
SYSTEMS, APPARATUSES AND METHODS FOR DYNAMIC VOLTAGE AND FREQUENCY CONTROL OF COMPONENTS USED IN A COMPUTER SYSTEM
Granted: March 1, 2012
Application Number:
20120054503
Embodiments of the present disclosure include systems, apparatuses, and methods for dynamic frequency and voltage control of components used in a computer system. A system includes a processor voltage regulator and a system clock generator directly operably with each other. The processor voltage regulator provides a core voltage signal to a processor, and is configured to detect a present processor load state of the processor. The system clock generator is for providing a system clock…
METHODS AND APPARATUSES FOR CLOCK DOMAIN CROSSING
Granted: February 16, 2012
Application Number:
20120038398
Clock-domain-crossing systems and methods include an integrator that accumulates input samples over multiple clock cycles in a first clock domain to generate an accumulation result. Clock-domain-crossing circuitry samples the accumulation result in the first clock domain after each of a repeating accumulation count to generate a first domain accumulation. The first domain accumulation is sampled in a second clock domain after a time delay to generate a second domain accumulation. The…
Apparatuses and methods for a voltage level shifting
Granted: January 5, 2012
Application Number:
20120001672
Level shifting circuits and a related method are disclosed herein. An embodiment of the present invention includes a voltage level shifter, comprising a first pull up transistor coupled to a high voltage signal and a first pull down transistor coupled between the first pull up transistor and a low voltage signal and controlled by an input signal. The voltage level shifter further includes a first bias transistor serially coupled between the first pull up transistor and the first bias…
METHODS AND APPARATUSES FOR FLEXIBLE AND HIGH PERFORMANCE DIGITAL SIGNAL PROCESSING
Granted: September 22, 2011
Application Number:
20110231463
A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor…
METHODS AND APPARATUSES FOR CORDIC PROCESSING
Granted: September 15, 2011
Application Number:
20110225222
A CORDIC engine includes an N-stage CORDIC processor for performing N micro-iterations of a CORDIC algorithm and generating a 3-vector CORDIC output responsive to a 3-vector CORDIC input. A counter counts a number of M macro-iterations for the CORDIC algorithm and indicates a start of the cycle iterations. A multiplexer selects an input to the N-stage CORDIC processor as the 3-vector CORDIC input at the start of the cycle iterations or the 3-vector CORDIC output at other times. The…
APPARATUSES AND METHODS FOR PHYSICAL LAYOUTS OF ANALOG-TO-DIGITAL CONVERTERS
Granted: September 1, 2011
Application Number:
20110210879
Physical layouts of integrated circuits are provided, which may include an analog-to-digital converter including a plurality of comparators. Individual transistors of each comparator of the plurality are arranged in a one-dimensional row in a first direction. Neighboring comparators of the plurality of comparators are positioned relative each other in an abutting configuration in a second direction orthogonal to the first direction. The plurality of comparators may include multiple,…
APPARATUSES AND METHODS FOR MULTIPLE-OUTPUT COMPARATORS AND ANALOG-TO-DIGITAL CONVERTERS
Granted: September 1, 2011
Application Number:
20110210878
An analog-to-digital converter with comparators with multiple, inter-coupled, outputs is provided, which may be also called a Benorion Analog-to-Digital Converter (ADC) or a Benorion Converter. The analog-to-digital converter includes a plurality of comparators operably coupled for receiving an analog input signal and configured for comparing the analog input signal with a plurality of voltage reference signals. Each comparator of the plurality is configured for generating a plurality of…
SYSTEMS, DEVICES, AND METHODS FOR PROVIDING BACKUP POWER TO A LOAD
Granted: August 18, 2011
Application Number:
20110198931
Systems, devices, and methods for providing backup power to a load are disclosed. A power converter may comprise a capacitor array comprising a plurality of capacitors and configured to store a charge from an input during a charge mode of operation and provide a charge to an output during a discharge mode of operation. Further, the power converter may comprise a controller configured to selectively couple the capacitor array to the input during a portion of the charge mode of operation…
High Speed Switch With Data Converter Physical Ports And Processing Unit
Granted: July 14, 2011
Application Number:
20110170619
An integrated circuit chip implements a high-speed switch that includes: a switch fabric; control logic that controls the transmission of digital signals through the switch fabric; a transceiver block comprising one or more transceivers, each transmitting digital signals between the control logic and a corresponding external device; a data converter physical interface comprising one or more data converters, each performing a conversion between analog and digital signals, wherein digital…
High Speed Switch With Data Converter Physical Ports
Granted: July 14, 2011
Application Number:
20110170577
A high-speed switch that includes a switch fabric, and both high-speed serial ports and data converter physical ports. A first set of data converter physical ports may perform analog-to-digital conversions, such that an external analog signal may be converted to a digital input signal on the switch. The converted digital input signal may then be routed through the switch fabric in accordance with a serial data protocol. A second set of data converter physical ports may perform…
Monolithic Clock Generator and Timing/Frequency Reference
Granted: July 14, 2011
Application Number:
20110169585
In various embodiments, the invention provides a clock generator and/or a timing and frequency reference, with multiple operating modes, such power conservation, clock, reference, and pulsed modes. The various apparatus embodiments include a resonator adapted to provide a first signal having a resonant frequency; an amplifier; a temperature compensator adapted to modify the resonant frequency in response to temperature; and a process variation compensator adapted to modify the resonant…
Analog/Digital Or Digital/Analog Conversion System Having Improved Linearity
Granted: June 23, 2011
Application Number:
20110148675
A digital-to-analog converter (DAC) circuit includes a least significant bit (LSB) set of capacitors, each commonly coupled to an LSB node, and a most significant bit (MSB) set of capacitors, each coupled to an MSB node. A section-coupling capacitor couples the LSB and MSB nodes. The LSB node exhibits a parasitic capacitance, which tends to introduce a jump error voltage. Digital input signals are applied to the LSB and MSB capacitors, and in response, an analog output signal is…
APPARATUSES AND METHODS FOR A LEVEL SHIFTER WITH REDUCED SHOOT-THROUGH CURRENT
Granted: May 19, 2011
Application Number:
20110115541
A level shifting circuit with reduced shoot-through current includes an output circuit comprising high-voltage devices with a pull up circuit configured for pulling up a voltage on an output signal to a high voltage responsive to a high-side control signal. The output circuit may also include a pull down circuit configured for pulling down the voltage on the output signal to a low voltage in responsive to a low-side control signal. The level shifting circuit can also include a high-side…
HIGH SPEED CHIP SCREENING METHOD USING DELAY LOCKED LOOP
Granted: April 28, 2011
Application Number:
20110098977
A voltage controlled delay line (VCDL) for measuring the maximum speed of a chip includes a first input configured to receive a reference clock signal, a first output configured to output an output clock signal, and a second input configured to receive a phase error signal representing a phase delay between the reference and output clock signals. A register stores a delay code applied by the VCDL to the reference clock signal to delay the reference clock signal to generate the output…
Method and Apparatus of ATE IC Scan Test Using FPGA-Based System
Granted: March 31, 2011
Application Number:
20110078525
An apparatus and a method for enhancing the use of automated test equipment (ATE), are presented. The apparatus comprises a test load board that mounts a plurality of devices to be tested (DUTs), and a daughter card communicating with the test board and the ATE, testing each of the plurality of devices, and providing test results to the ATE. The method comprises mounting a plurality of devices to be tested on the test load board, using the daughter card to communicate with the test board…
