APPARATUSES AND METHODS FOR A SCR-BASED CLAMPED ELECTROSTATIC DISCHARGE PROTECTION DEVICE
Granted: March 17, 2011
Application Number:
20110063764
A SCR-based based electrostatic discharge protection device with a shunt path is provided. The shunt path operates at a low resistance when an enabling signal of the shunt path is asserted and a high resistance when the enabling signal is negated. The shunt path connects the cathode and the gate of the silicon-controlled rectifier, and provides a conductive path for displacement current from a parasitic capacitance when the shunt path is enabled, such as when power is provided to the…
High Voltage Switch Utilizing Low Voltage MOS Transistors with High Voltage Breakdown Isolation Junctions
Granted: March 10, 2011
Application Number:
20110057714
A high voltage switch having first and second states includes an input receiving an input voltage that is greater than a supply voltage. Each of first, second, and third MOS structures of a first conductivity type has a gate, a source, and a drain. The sources and drains of each of the MOS structures are electrically coupled in series between the input and ground. An output is electrically coupled to the input. When the switch is in the first state, the gate of the first MOS structure is…
INTERLEAVED/ALL-PHASE MODE SWITCHED PWM SYSTEM
Granted: January 20, 2011
Application Number:
20110012574
A multi-phase power switching converter having first and second states includes a pulse width modulator having an output, a converter output providing an output signal, and a plurality of drivers, each having an output electrically coupled to the converter output and an input. When the converter is in the first state where a duty cycle of the converter is less than or equal to 100 divided by the number of drivers, each of the driver inputs is configured to be sequentially electrically…
Charge Pump Linearization Technique For Delta-Sigma Fractional-N Synthesizers
Granted: December 30, 2010
Application Number:
20100327981
A delta-sigma fractional-N frequency synthesizer having a charge pump with error canceling circuitry eliminates a non-linear term from the charge pump transfer function. The charge pump includes a matched pair of charging current sources, each supplying a first current IP1 to a common node, when enabled. The charge pump also includes a matched pair of discharging current sources, each sinking a second current IN1 from the common node, when enabled. The error canceling circuitry includes…
METHODS AND APPARATUSES FOR INCREMENTAL BANDWIDTH CHANGES RESPONSIVE TO FREQUENCY CHANGES OF A PHASE-LOCKED LOOP
Granted: December 23, 2010
Application Number:
20100321074
In a phase-locked loop, a desired change in frequency is indicated. The phase-locked loop locks to the new frequency and a loop bandwidth of the phase-locked loop is changed. In changing the loop bandwidth, a frequency adjustment signal to a voltage-controlled oscillator may include a voltage spike. The voltage spike is reduced by detecting a lock when the reference clock and a feedback clock reach a same frequency, then waiting for a time delay after the detecting the lock, and…
DYNAMIC PHASE TRACKING USING EDGE DETECTION
Granted: November 25, 2010
Application Number:
20100296615
Methods and apparatus of phase tracking are described. Decisions regarding phase location of an oversampled portion of a data signal are based on the content of the data signal. In one example, a phase decision threshold is dynamically variable based on whether a predetermined number of edges is detected in the data signal.
Ternary Content Addressable Memory Having Reduced Leakage Effects
Granted: October 28, 2010
Application Number:
20100271854
A column of ternary content addressable memory (TCAM) cells includes a bit line pair that is twisted at a location at or near the center of the column. Data is written to (and read from) TCAM cells located above the twist location with a first bit line polarity. Data is written to (and read from) TCAM cells located below the twist location with a second bit line polarity, opposite the first bit line polarity. As a result, read leakage currents introduced by TCAM cells storing ‘Don't…
Content Addressable Memory Having Bidirectional Lines That Support Passing Read/Write Data And Search Data
Granted: September 16, 2010
Application Number:
20100232194
A CAM column structure includes an interface that drives search data to a plurality of CAM cells via a search line pair. The CAM cells are divided into sections, each section including: a set of CAM cells, a bit line pair coupled to the set of CAM cells, a sense amplifier coupled to the bit line pair, a tri-state read buffer configured to drive read data from the sense amplifier to the search line pair, and a pair of tri-state write buffers configured to drive write data from the search…
Content Addressable Memory (CAM) Array Capable Of Implementing Read Or Write Operations During Search Operations
Granted: September 16, 2010
Application Number:
20100232195
A read operation and a search operation are performed during the same cycle within a CAM system including a CAM array by: (1) forcing a non-matching condition to exist in the row of the CAM array selected for the read operation, (2) comparing the read data value with the search data value outside of the CAM array to determine whether a match exists, and (3) prioritizing the results of the search operation performed within the CAM array and the results of the comparison performed outside…
Separate CAM Core Power Supply For Power Saving
Granted: February 25, 2010
Application Number:
20100046265
A CAM system includes an integrated circuit chip having: logic & control circuitry, a CAM cell array, read/write access circuitry that performs read and write accesses to the CAM cell array, comparison access circuitry that performs comparison operations to the CAM cell array, a first voltage supply pad coupled to the read/write access circuitry; and a second voltage supply pad coupled to the comparison access circuitry. A first voltage supply, external to the integrated circuit…
IMPEDANCE MATCHING LOGIC
Granted: January 14, 2010
Application Number:
20100007373
An impedance matching logic generates code values that define pull-up and pull-down transistors to be enabled with output buffers. The output buffers store the code values using a two-stage latch configuration, such that updated code values are always stored within the output buffer, even if the output buffer is driving an output signal when the updated code values are received. The impedance matching logic uses previously determined code values to shorten the time required to calculate…
Multi-Package Ball Grid Array
Granted: December 31, 2009
Application Number:
20090321905
A multi-package module that includes a multi-layer interconnect structure, a housing structure attached to the multi-layer interconnect structure, and a plurality of integrated circuit packages inserted into slots in the housing structure, and placed into contact with the multi-layer interconnect structure. The integrated circuit packages can be removed from the slots in the housing structure, thereby enabling testing and/or replacement of the integrated circuit packages.
INPUT CLOCK DETECTION CIRCUIT FOR POWERING DOWN A PLL-BASED SYSTEM
Granted: October 15, 2009
Application Number:
20090256600
An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the…
CONTENT DRIVEN PACKET SWITCH
Granted: September 24, 2009
Application Number:
20090238184
A packet switch routes data packets based on both packet headers and data payloads in the data packets. The packet switch receives data packets, identifies a destination port of the packet switch for each data packet based on a packet header of the data packet, and routes the data packet to the destination port. Additionally, the packet switch selects data packets among the data packets received by the packet switch based on the data payloads of the received data packets, identifies a…
Method To Support Flexible Data Transport On Serial Protocols
Granted: September 10, 2009
Application Number:
20090225769
A serial buffer transports packets through queues capable of operating in a packet mode or a raw data mode. In packet mode, entire packets are stored in a queue. In raw data mode, packet header/delimiter information is not stored in the queue (only packet data is stored). Packets can be transferred out of a queue in response to a slave read request. The serial buffer constructs a packet header in response to the slave read request, and retrieves a specified amount of packet data from the…
Method To Support Lossless Real Time Data Sampling And Processing On Rapid I/O End-Point
Granted: September 10, 2009
Application Number:
20090225770
A serial buffer monitors an incoming stream of packets to identify single missing packets and multiple consecutive missing packets. Upon detecting multiple consecutive missing packets, an interrupt is generated, thereby stopping the data transfer. Upon detecting a single missing packet, a single missing packet identifier is inserted into the packet header of the packet that resulted in identification of the single missing packet. The incoming packets, including any inserted single…
Serial Buffer To Support Reliable Connection Between Rapid I/O End-Point And FPGA Lite-Weight Protocols
Granted: September 10, 2009
Application Number:
20090225775
A serial buffer includes a first port configured to implement an serial rapid I/O (sRIO) protocol and a second port configured to implement a Lite-weight serial (Lite) protocol. SRIO packets received on the first port are translated into Lite request packets compatible with the Lite protocol. The Lite request packets are transmitted to the second port. Lite response packets compatible with the Lite protocol are returned to the second port in response to the Lite request packets. The Lite…
Protocol Translation In A Serial Buffer
Granted: September 10, 2009
Application Number:
20090228621
A serial buffer includes a first port configured to operate in accordance with a first serial protocol and a second port configured to operate in accordance with a second serial protocol. A first translation circuit of the serial buffer allows packets received on the first port to be translated to the second serial protocol, and then transferred to the second port. A second translation circuit of the serial buffer allows packets received on the second port to be translated to the first…
Serial Buffer To Support Rapid I/O Logic Layer Out Of order Response With Data Retransmission
Granted: September 10, 2009
Application Number:
20090228630
Within a serial buffer, request packets are written to available memory blocks of a memory buffer, which are identified by a free buffer pointer list. When a request packet is written to a memory block, the memory block is removed from the free buffer pointer list, and added to a used buffer pointer list. Memory blocks in the used buffer pointer list are read, thereby transmitting the associated request packets from the serial buffer. When a request packet is read from a memory block,…
Power Management On sRIO Endpoint
Granted: September 10, 2009
Application Number:
20090228733
Clock signals used to operate core receive logic and core transmit logic within a serial buffer are dynamically enabled and disabled to minimize power consumption. A physical layer interface and an event monitor are continuously enabled to identify the start of incoming transactions. Upon detecting the start of an incoming transaction, the event monitor activates a packet retry signal, and also initiates generation of a receive clock signal within the serial buffer. By the time that the…
