Cam circuit with error correction
Granted: January 9, 2003
Application Number:
20030007408
A CAM circuit including a RAM array, a CAM array, a control/interface circuit, and an error detection and correction (EDC) circuit. The control/interface circuit systematically writes data from the RAM array to the CAM array, thereby preventing soft errors by continually refreshing data stored in the CAM array. The RAM array also stores check bits for each data word that can be generated by the EDC circuit when the data words are initially written to the CAM circuit. During the refresh…
Content addressable memory array having flexible priority support
Granted: January 2, 2003
Application Number:
20030005146
A method for processing addresses having variable prefix lengths, including (1) applying an input address to a plurality of CAM blocks; (2) assigning different sets of CAM blocks to store prefixes of different lengths; (3) generating a hit signal and an index signal with each of the CAM blocks in response to the input address; (4) programming a plurality of routing values; (5) routing the hit signals to a priority encoder in an order determined by the routing values; (6) generating an…
Die bonding apparatus with automatic die and lead frame image matching system
Granted: December 5, 2002
Application Number:
20020181758
A vision system that compares the captured images of a die and a lead frame loaded in a die bonding apparatus with stored images thereof, and interrupts the die bonding process when the captured images fail to match the stored images. The images are directed to distinctive features of the die (e.g., the positioning and size of the die bonding pads) and lead frame (e.g., positioning and size of the leads) that differ between various die and lead frames having similar sizes. A first camera…
CAM circuit with radiation resistance
Granted: October 31, 2002
Application Number:
20020159320
A CAM circuit including a RAM array, a CAM array, and a control circuit that systematically writes data from the RAM array to the CAM array, thereby preventing soft errors by continually restoring data that has been corrupted by radiation. The RAM and CAM arrays can be formed on the same substrate, but are preferably fabricated on separate substrates and mounted in a single package or on a PCB. Both the CAM and RAM can be formed using any conventional memory type (e.g., SRAM, DRAM,…
Method for fabricating dual-gate structure
Granted: December 20, 2001
Application Number:
20010052626
A dual-gate semiconductor structure including a first polysilicon layer that has a p-type region and an n-type region. The p-type region overlies the channel region of a p-channel transistor, and the n-type region overlies the channel region of an n-channel transistor. A second polysilicon layer is formed directly on the first polysilicon layer, and exhibits good adhesion with the first polysilicon layer. A metal silicide layer is deposited on the second polysilicon layer. The second…
