Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system
Granted: January 26, 2006
Application Number:
20060018177
A method of operating a multi-queue device, including: (1) storing a plurality of read (write) count pointers, wherein each of the read (write) count pointers is associated with a corresponding queue of the multi-queue device, (2) providing a read (write) count pointer associated with a present queue to read (write) flag logic, (3) adjusting the read (write) count pointer associated with the present queue in response to each read (write) operation performed by the present queue, (4)…
Synchronization of active flag and status bus flags in a multi-queue first-in first-out memory system
Granted: January 26, 2006
Application Number:
20060020741
A flag logic circuit includes a first comparator configured to generate a first flag value associated with an active read queue of a multi-queue memory device, and a second comparator configured to generate a second flag value associated with an active write queue of the multi-queue memory device. A dual-port memory is adapted to store a flag value for each queue of the multi-queue memory device. The dual-port memory has a first write port configured to receive the first flag value and a…
Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory system
Granted: January 26, 2006
Application Number:
20060020742
A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory device. Flag values are routed from the first stage memory to a flag status bus having a width N in the manner described below. A status bus control circuit receives a signal that identifies the number of queues M actually used by the multi-queue memory device, and in response, generates a repeating…
Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory system
Granted: January 26, 2006
Application Number:
20060020743
A multi-queue FIFO memory device that uses existing pins of the device to load a desired number of queues (N) into a queue number register is provided. The queue number register is coupled to a queue size look-up table (LUT), which provides a queue size value in response to the contents of the queue number register. The queue size value indicates the amount of memory (e.g., the number of memory blocks) to be included in each of the N queues. The queue size value is provided to a queue…
Partial packet read/write and data filtering in a multi-queue first-in first-out memory system
Granted: January 26, 2006
Application Number:
20060020761
A multi-queue memory system is configured to operate in a packet mode. Each packet includes a SOP (start of packet) marker and an EOP (end of packet) marker. A packet status bit (PSB), is used to implement the packet mode. The packet status bit enables partial packet write and partial packet read operations, such that a queue switch can be performed in the middle of packet write or packet read operations. The packet status bit also enables data filtering to be performed between an…
Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system
Granted: January 26, 2006
Application Number:
20060018176
In a multi-queue memory system, a plurality of read count pointers (one for each queue) are stored in a read address file, and used to generate empty flags. A read count pointer associated with a first queue is retrieved from the read address file, and it is determined whether the first queue should be available for a re-read operation. If so, the retrieved read count pointer is stored as a first read mark value. The read count pointer is incremented in response to each read operation…
DRAM-based CAM cell with shared bitlines
Granted: July 14, 2005
Application Number:
20050152199
A CAM cell is disclosed that includes a comparator and two three-transistor (3T) DRAM cells connected to a pair of associated bit lines. Data is stored using intrinsic capacitance of each 3T DRAM cell, and is applied to the gate terminal of a pull-down transistor of the comparator. During refresh operations, inverted data values are written onto the bit lines, and subsequently written from the bit lines to the 3T DRAM cells. In ternary embodiments, an inverting refresh circuit is used to…
Nitrogen implementation to minimize device variation
Granted: May 5, 2005
Application Number:
20050093109
A rapid thermal nitridation (RTN) process produces a nitrogen concentration gradient in an oxynitride layer to compensate for transistor threshold voltage effects from a thickness gradient in the oxynitride layer. The nitrogen concentration gradient is selected to allow greater dopant penetration through thicker gate dielectrics in PMOS transistors formed using the oxynitride layer. Any increases in threshold voltage due to thicker gate dielectrics are counteracted by corresponding…
Precise voltage/current reference circuit using current-mode technique in CMOS technology
Granted: February 17, 2005
Application Number:
20050035814
A voltage/current reference circuit includes a first bipolar transistor and a second bipolar transistor that exhibit a first voltage drop VBE1 and a second voltage drop VBE2, respectively. A first resistor, having a resistance R1, is configured to draw a first current equal to (VBE1?VBE2)/R1. A second resistor, having a resistance R2, is configured to draw a second current equal to VBE1/R2. A first transistor supplies the first and second currents to the first and second resistors. A…
Random access memory architecture and serial interface with continuous packet handling capability
Granted: November 25, 2004
Application Number:
20040233906
A random access memory architecture and method of handling data packets is described. According to embodiments of the invention, an apparatus includes a first processing unit for receiving serial data input, a switch, and a plurality of serially connected random access memory devices. The random access memory devices transmit data packets and commands via write input ports, write output ports, read input ports, and read output ports. A method for routing data includes receiving serial…
CAM circuit with radiation resistance
Granted: October 21, 2004
Application Number:
20040208034
A CMOS CAM circuit an array of CAMs formed on a p-type substrate. Each CAM cell includes a logic portion and an SRAM cell, both having at least one n-channel transistor formed in a p-type well on the p-type substrate. An n-type doped layer is formed between the p-type well region and the p-substrate. The doped layer and well region are maintained at a voltage potential that is between a threshold voltage and a breakdown voltage defined the PN junction formed at their interface. The…
Etch stop layer for use in a self-aligned contact etch
Granted: June 10, 2004
Application Number:
20040110346
A self-aligned contact, and a method for fabricating the same, are provided. A conductive element having an overlying hydrogen silsesquioxane (HSQ)-based dielectric cap is formed over a semiconductor substrate. Dielectric sidewall spacers are then formed adjacent to sidewalls of the conductive element and the HSQ-based dielectric cap. A HSQ-based dielectric layer is formed over the resulting structure, and an inter-layer dielectric layer, such as TEOS, is formed over the HSQ-based…
Method of performing deficit round-robin scheduling and structure for implementing same
Granted: December 18, 2003
Application Number:
20030231590
A deficit round-robin scheduler including a round-robin table configured to store a plurality of cycle link lists, wherein each cycle link list includes a head flow identification (FLID) value identifying a first flow of the cycle link list, and a tail FLID value identifying a last flow of the cycle link list. A flow table is provided having a plurality of flow table entries, wherein each of the flow table entries is associated with a corresponding flow, and therefore has a corresponding…
Use of hashed content addressable memory (CAM) to accelerate content-aware searches
Granted: December 18, 2003
Application Number:
20030233514
A server is provided having a port for receiving a data request that includes an identifier (e.g., an HTTP request that includes a URL). Recognition logic is provided to extract the identifier, using delimiters present in the data request. Padding logic fixes the length of the identifier at a predetermined length (e.g., by adding zeros to the end of the identifier), thereby creating a fixed-length identifier. Hashing logic is provided to perform a hashing function on the fixed-length…
Hardware hashing of an input of a content addressable memory (CAM) to emulate a wider CAM
Granted: December 18, 2003
Application Number:
20030233515
An integrated circuit chip is provided having a port for receiving a character string. A hardware hashing circuit on the integrated circuit chip is configured to perform a hashing function on the character string, thereby creating a hashed output value. A binary content addressable memory (CAM) array on the integrated circuit chip is coupled to receive the hashed output value. The binary CAM array provides an index value in response to the hashed output value if the hashed output value…
CAM circuit with radiation resistance
Granted: December 11, 2003
Application Number:
20030227788
A CMOS CAM circuit an array of CAMs formed on a p-type substrate. Each CAM cell includes a logic portion and an SRAM cell, both having at least one n-channel transistor formed in a p-type well on the p-type substrate. An n-type doped layer is formed between the p-type well region and the p-substrate that attracts electron-hole pairs formed by alpha particles, thereby preventing soft errors. Alternatively, the logic portions and SRAM cells have p-channel transistors formed in n-type wells…
CAM CIRCUIT WITH SEPARATE MEMORY AND LOGIC OPERATING VOLTAGES
Granted: December 11, 2003
Application Number:
20030227789
A CAM circuit utilizes a relatively high operating voltage to control the memory portion of each CAM cell, and a relatively low operating voltage to control at least some of the logic portions of each CAM circuit. The CAM cell memory portion includes a memory (e.g., SRAM) cell controlled by a word line to store data values transmitted on complementary bit lines. The CAM cell logic portion includes a comparator that compares the stored data values with an applied data value transmitted on…
SRAM System having very lightly doped SRAM load transistors for improving SRAM cell stability and method for same
Granted: September 18, 2003
Application Number:
20030173625
A static random access memory (SRAM) cell is given increased stability and latch-up immunity by fabricating the PMOS load transistors of the SRAM cell to have a very low drain/source dopant concentration. The drain/source regions of the PMOS load transistors are formed entirely by a P−− blanket implant. The PMOS load transistors are masked during subsequent implant steps, such that the drain/source regions of the PMOS load transistors do not receive additional P-type (or…
Lead formation, assembly strip test, and singulation system
Granted: January 30, 2003
Application Number:
20030020509
An integral system for testing integrated circuits (ICs) mounted on an assembly strip after lead formation and before separation from the assembly strip. The ICs are arranged in rows and columns on each assembly strip such that the sides of each IC are connected to leads extending from the assembly strip, and the ends of each IC are held by the assembly strip. The strips are loaded into the system and passed to a first station at which leads are cut and formed while the ends of each IC…
LEAD FORMATION, ASSEMBLY STRIP TEST AND SINGULATION METHOD
Granted: January 30, 2003
Application Number:
20030022405
A method for testing integrated circuits (ICs) mounted on an assembly strip after lead formation and before separation from the assembly strip. The ICs are arranged in rows and columns on each assembly strip such that the sides of each IC are connected to leads extending from the assembly strip, and the ends of each IC are held by the assembly strip. The strips are loaded into the system and passed to a first station at which leads are cut and formed while the ends of each IC remain…
