Adaptive high-speed current-steering logic (HCSL) drivers
Granted: December 5, 2017
Patent Number:
9838016
A packaged integrated circuit device includes a first driver, which has a first pair of differential output terminals and a first common-mode sensing terminal, and a second driver, which has a second pair of differential output terminals and a second common-mode sensing terminal. The second driver can be a smaller scaled replica of the first driver. A comparator and a reference signal generator are provided. The comparator is configured to compare first and second common-mode voltage…
Apparatuses and wireless power transmitters having multiple transmit coils and related method
Granted: December 5, 2017
Patent Number:
9837864
A wireless power transmitter may include a bridge inverter and a plurality of parallel paths operably coupled to the bridge inverter. Each path includes a resonance tank including a transmit coil coupled with at least one resonance capacitor, a first switch serially coupled with the resonance tank and switching node A of the bridge inverter, a first clamping element in parallel with the first switch, a second switch serially coupled with the resonance tank and switching node B of the…
Extending beamforming capability of a coupled voltage controlled oscillator (VCO) array during local oscillator (LO) signal generation through a circular configuration thereof
Granted: December 5, 2017
Patent Number:
9837714
A method includes separating phase of Local Oscillator (LO) signals generated by individual Voltage Controlled Oscillators (VCOs) of a coupled VCO array through varying voltage levels of voltage control inputs thereto. The method also includes coupling the individual VCOs of the coupled VCO array to one another in a closed, circular configuration to increase phase difference between the phase separated LO signals generated by the individual VCOs compared to a linear configuration of the…
Apparatuses having different modes of operation for inductive wireless power transfer and related method
Granted: December 5, 2017
Patent Number:
9837203
An inductive wireless power enabled device may comprise a transceiver including a plurality of switches coupled with a resonant tank, and control logic configured to drive the plurality of switches to operate the resonant tank in one of a transmit mode and a receive mode. Another inductive wireless power enabled device may comprises a transceiver including a plurality of switches coupled with a resonant tank. The transceiver may be configured to both transmit a wireless power signal…
Fast-response hybrid lock detector
Granted: November 28, 2017
Patent Number:
9831882
The invention concerns an apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate an enable signal in response to (i) a comparison of a width of an up pulse and a pre-determined width and (ii) a comparison of a width of a down pulse and the pre-determined width. The up pulse and the down pulse may be generated in response to a comparison of a feedback signal and a reference signal. The enable signal may be active when both the…
System and method for wireless power transfer using a two half-bridge to one full-bridge switchover
Granted: November 7, 2017
Patent Number:
9812903
A system and method of wireless power transfer using a two half-bridge to one full-bridge switchover includes a wireless power transfer system. The wireless power transfer system includes a controller, first and second transmitters coupled to the controller, the first and second transmitters being coupled to one another by an electrical connection, and a switch coupled between the electrical connection and a voltage rail. When the switch is closed, the controller operates the first and…
Asymmetric on-state resistance driver optimized for multi-drop DDR4
Granted: October 17, 2017
Patent Number:
9794087
An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a memory signal that transfers read data across a read line to a memory controller. The plurality of control registers may be configured to enable one or more of the driver circuits. A pull up strength and a pull down strength of the memory signal may be configured in response to how many of the plurality of driver circuits are enabled.…
Overvoltage protection circuits and methods of operating same
Granted: October 17, 2017
Patent Number:
9793708
Overvoltage protection circuits include a combination of an overvoltage detection circuit and a voltage clamping circuit that inhibits sustained overvoltage conditions. An overvoltage detection circuit can include first and second terminals electrically coupled to first and second power supply signal lines, respectively. This overvoltage detection circuit may be configured to generate a clamp activation signal (CAS) in response to detecting an excessive overvoltage between the first and…
Packaged oscillators with built-in self-test circuits that support resonator testing with reduced pin count
Granted: October 17, 2017
Patent Number:
9791503
Packaged integrated circuit devices include an oscillator circuit having a resonator (e.g., quartz crystal, MEMs, etc.) associated therewith, which is configured to generate a periodic reference signal. A built-in self-test (BIST) circuit is provided, which is selectively electrically coupled to first and second terminals of the resonator during an operation by the BIST circuit to test at least one performance characteristic of the resonator, such as at least one failure mode. These test…
Phase shift based improved reference input frequency signal injection into a coupled voltage controlled oscillator (VCO) array during local oscillator (LO) signal generation to reduce a phase-steering requirement during beamforming
Granted: October 3, 2017
Patent Number:
9780449
A method includes injecting a reference input signal into each Voltage Controlled Oscillator (VCO) of a number of VCOs forming a coupled VCO array to reduce a level of injection energy required therefor. The reference input signal is configured to control operating frequency of the coupled VCO array. The method also includes utilizing a phase shift circuit: between individual VCOs of the coupled VCO array and/or in a path of injection of the reference input signal into one or more VCO(s)…
Apparatuses and methods for over-current protection of DC-DC voltage converters
Granted: July 18, 2017
Patent Number:
9712041
A peak current protection circuit includes a current sensing circuit configured to sense an operating current of a DC-DC converter, and an over-current detector operably coupled with the current sensing circuit. The over-current detector is configured to generate an over-current detect signal at a peak current limit that is that is independent of a voltage level of an output signal of the DC-DC converter. A method for providing over-current protection for a DC-DC converter includes…
Integrated low voltage differential signaling (LVDS) and high-speed current steering logic (HCSL) circuit and method of use
Granted: July 4, 2017
Patent Number:
9698787
An integrated circuit includes a low voltage differential signaling (LVDS) output circuit, a high-speed current steering logic (HCSL) output circuit, a bias control circuit, a programmable voltage reference circuit coupled to the bias control circuit, an output stage circuit coupled to the HCSL output circuit, a first plurality of switches to switchably couple the bias control circuit to the LVDS output circuit, a second plurality of switches to switchably couple the bias control circuit…
Programmable low power high-speed current steering logic (LPHCSL) driver and method of use
Granted: June 27, 2017
Patent Number:
9692394
An integrated circuit comprising, a voltage regulator circuit and a programmable low power high-speed current steering logic (LPHCSL) driver circuit coupled to a common supply voltage. The voltage regulator circuit includes a native source follower transistor having a negative threshold voltage to provide more headroom for the voltage regulator to operate. The LPHCSL driver circuit includes a plurality of selectable output driver legs and a plurality of programmable resistors. The…
Fractional divider using a calibrated digital-to-time converter
Granted: June 13, 2017
Patent Number:
9678481
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a…
Apparatus and method for a switching power converter
Granted: June 6, 2017
Patent Number:
9673638
A charging converter includes a plurality of switches configured to switchably operate to either step up an input voltage or step down the input voltage and generate a charging voltage on a second terminal to charge to a rechargeable storage unit, and control logic configured to operate the plurality of switches in one of a step up mode and a step down mode based on a determination of a voltage level of the input voltage relative to the desired charging voltage. A method includes…
System and method for synchronous rectification with enhanced detection of small currents
Granted: May 30, 2017
Patent Number:
9667168
A system and method of synchronous rectification includes a synchronous rectifier circuit. The synchronous rectifier circuit includes a direct current (DC) load coupled between a DC output node and a ground node, an alternating current (AC) source applying an AC waveform to an AC input node, an upper switch coupled between the DC output node and the AC input node, and a lower switch coupled between the AC input node and the ground node. In a first state, the upper switch is turned on and…
Calibration method and apparatus for phase locked loop circuit
Granted: May 16, 2017
Patent Number:
9654121
An integrated circuit apparatus for calibrating a phase locked loop (PLL) circuit that includes a phase comparator configured to receive a reference clock signal and a feedback clock signal and generate a phase error signal, a variable frequency oscillator configured for receiving the phase error signal and generating a corresponding fast clock signal at an output of the variable frequency oscillator, and a divider that is configured to divide the fast clock signal by a divisor (N) so as…
Asymmetrical emphasis in a memory data bus driver
Granted: May 16, 2017
Patent Number:
9653147
An apparatus includes an interface and a circuit. The interface may be configured to generate a memory signal that carries read data from a memory channel. The circuit may be configured to modify a read signal that transfers the read data across a read line to a memory controller. A filter may delay the memory signal to generate a delayed signal. A driver generally amplifies the memory signal to generate the read signal. The driver may modify the read signal with a de-emphasis on each…
Testability/manufacturing method to adjust output skew timing
Granted: May 2, 2017
Patent Number:
9640278
An apparatus includes an output driver circuit and a trimming circuit. The output driver circuit may be configured to (i) receive an input signal and a first control signal and (ii) generate an output signal. The output signal may be a delayed version of the input signal. A length of delay between the input signal and the output signal is determined in response to the first control signal. The trimming circuit may be configured to generate the first control signal in response to a second…
Methods and apparatus for transmitting data over a clock signal
Granted: April 18, 2017
Patent Number:
9628255
A method of operating a clock circuit can include transmitting a clock signal from a transmitter of a first system to a receiver of a second system, where a first repeating edge of a clock cycle of the clock signal repeats at a predetermined constant frequency within the clock signal to synchronize operations of the second system, and varying, by the first system, a second edge within the clock cycle of the clock signal to transmit a data transmission within the clock signal.
