Initiating operation of a timing device using a read only memory (ROM) or a one time programmable non volatile memory (OTP NVM)
Granted: November 15, 2016
Patent Number:
9495285
The present invention provides a method and a programmable timing device that includes a timing device circuit for generating at least one timing signal, a static random access memory (SRAM) coupled to the timing device circuit, a read only memory (ROM) having a first timing device configuration stored therein, a one time programmable non volatile memory (OTP NVM) for storing a second timing device configuration and selection logic. The selection logic includes an output coupled to the…
Integrated circuits having multiple digitally-controlled oscillators (DCOs) therein that are slaved to the same loop filter
Granted: November 8, 2016
Patent Number:
9490828
A phase-locked loop (PLL) integrated circuit includes multiple digitally-controlled oscillators (DCOs), which are slaved to the same feedback loop filter. This PLL includes a frequency control circuit, which is configured to generate a control signal and is responsive to a first periodic reference signal (e.g., REFCLK). The plurality of DCOs include a corresponding plurality of independently-programmable fractional dividers, which are configured to generate a respective plurality of…
Low power driver with programmable output impedance
Granted: November 8, 2016
Patent Number:
9490805
A programmable low power driver permits an output impedance of the driver to be programmed. Programmability permits the driver output impedance to match an impedance of a transmission line that is connected thereto. The low power driver includes a first driver output and a plurality of driver legs. The programmable low power driver is configured to electrically couple one or more driver legs of the plurality of driver legs to the first driver output to establish an output impedance for…
Method and apparatus for controlling error and identifying bursts in a data compression system
Granted: November 1, 2016
Patent Number:
9485688
The method and apparatus of the present invention provides for the compression and decompression of data bursts wherein the propagation of synchronization errors is limited to a desired number of signal samples and the start of a burst boundary is identified. In accordance with the present invention, a method and apparatus are provided for compressing data in a communication system by receiving data bursts comprising a plurality of uncompressed data packets at a compressor of the…
Long-distance RapidIO packet delivery
Granted: November 1, 2016
Patent Number:
9485053
The present invention provides a RapidIO device that includes a switch fabric and a port coupled to the switch fabric. The port is configured to establish a LP-Serial link with RapidIO endpoints, add packet headers having the same acknowledgement identifier to a plurality of contiguous packets and generate a link cyclical redundancy check value for the plurality of contiguous packets having the same acknowledgement identifier, the link cyclical redundancy check code computed to include…
Methods and apparatus for synchronizing operations using separate asynchronous signals
Granted: October 25, 2016
Patent Number:
9479182
A method of synchronizing operations between integrated circuits can include transmitting a first clock signal from a first transmitter associated with a first integrated circuit of a first system, to a receiver associated with a second integrated circuit of a second system, receiving a second clock signal from a second transmitter associated with a third integrated circuit of the second system, receiving at the first system a first phase difference determined by the second system,…
Self-calibrating fractional divider circuits
Granted: October 25, 2016
Patent Number:
9479177
A fractional divider (FD) includes a multi-modulus divider (MMD), which generates a periodic output signal in response to: (i) a periodic reference signal (REFHF), and (ii) a modulus control signal having a value that sets a frequency division ratio (1/P, 1/(P+1)) to be applied to the periodic reference signal. A phase correction circuit is provided, which generates an FD output signal in response to the periodic MMD output signal and a corrected multi-bit phase correction control (CPCC)…
Integrated circuit device substrates having packaged inductors thereon
Granted: October 25, 2016
Patent Number:
9478599
An integrated circuit device includes an integrated circuit substrate having an at least two piece package thereon. The package has a sealed cavity therein and a patterned metal inductor in the cavity. The inductor has at least a first terminal electrically coupled to a portion of the integrated circuit substrate by an electrically conductive via, which extends at least partially through the package. The package, which may include a material selected from a group consisting of glass and…
Controlling operation of a timing device using an OTP NVM to store timing device configurations in a RAM
Granted: September 27, 2016
Patent Number:
9455045
The present invention provides a method and apparatus that includes a timing device circuit for generating a timing signal, a RAM coupled to the timing device circuit, an OTP NVM and selection logic. The RAM is operable upon receiving a burn address to read configuration data in the RAM beginning at the burn address and the OTP NVM is operable to burn the configuration data read from RAM into the OTP NVM. The OTP NVM is configured to read configuration data in the OTP NVM and the RAM is…
Apparatus, system, and method for detecting a foreign object in an inductive wireless power transfer system
Granted: September 20, 2016
Patent Number:
9450648
An inductive wireless power transfer system comprises a transmitter configured to generate wireless power signal to a coupling region in response to an input signal. The inductive wireless power transfer system's control logic is configured to determine an input power of the input signal. The control logic is configured to determine a presence of a foreign object within the coupling region in response to a comparison of the input power and an output power of an output signal of a…
Crystal oscillator fabrication methods using dual-deposition of mounting cement and dual-curing techniques
Granted: September 13, 2016
Patent Number:
9445536
A crystal oscillator fabrication method includes depositing mounting cement onto first and second mounting pads on a substrate to thereby define first and second electrode adhesion bumps. First and second electrodes of a crystal oscillator are electrically connected to the first and second mounting pads by contacting the first and second electrodes to the first and second electrode adhesion bumps and then curing the adhesion bumps. Next, mounting cement is deposited onto the first…
Methods of performing time-of-day synchronization in packet processing networks
Granted: September 13, 2016
Patent Number:
9444566
Methods of performing time-of-day synchronization in a packet processing network include accumulating timestamps transmitted in packets between master and slave devices, which are synchronized to respective master and slave clocks and separated from each other by the packet processing network. Operations are also performed to determine whether first timestamps accumulated in a first direction across the packet network demonstrate that a first packet delay variation (PDV) sequence…
Method and apparatus for using tester channel as device power supply
Granted: September 13, 2016
Patent Number:
9442167
A method and apparatus for using a tester channel as device power have been disclosed. By utilizing a tester channel output as an input, a voltage and current driver are used to boost the input which is followed by a current to voltage converter which can be used as a device power supply for a device under test. Additional tester channels may be used to sense and force voltages, measure currents, supply output voltage, and relay control, etc. for changing operation.
Integrated circuits having low power, low interference and programmable delay generators therein and methods of operating same
Granted: September 6, 2016
Patent Number:
9438252
A programmable delay generator includes a calibration circuit and a delay line responsive to a calibration control signal generated by the calibration circuit. The calibration circuit includes a digitally-controlled oscillator (DCO) having a first plurality of delay stages therein. A frequency of the DCO is set by the calibration control signal. The delay line includes a second plurality of delay stages that are replicas of the first plurality of delay stages. The calibration circuit may…
Methods and apparatuses for slew rate enhancement of amplifiers
Granted: August 30, 2016
Patent Number:
9431968
A circuit is disclosed to enhance slew rate of an amplifier. An amplifier includes an output, a first input, and a second input in a differential pair configuration. A slew rate enhancer includes a first slew rate enhancer and a second slew rate enhancer. The first slew direction enhancer is configured to detect a first slew rate condition in a first direction responsive to the first input and the second input and provide additional current for a first side of the differential pair of…
Monolithic composite resonator devices with reduced sensitivity to acceleration and vibration
Granted: August 30, 2016
Patent Number:
9431955
An integrated circuit device includes a pair of serially-connected crystal resonators arranged as a first crystal resonator, which is configured to preferentially support a fundamental resonance mode in response to an input signal, and a second crystal resonator, which is configured to preferentially support a third or higher overtone resonance mode in response to a signal generated at an output terminal of the first crystal resonator. A negative impedance converter (NIC) is also…
Apparatuses and related methods for charging control of a switching voltage regulator
Granted: August 30, 2016
Patent Number:
9431838
Charging systems and related methods are disclosed for switching voltage regulators. A charging controller may be configured to generate a control signal indicating a first level of an output current generated by a switching voltage regulator for charging an energy storage device, determine that an output voltage exceeded a predetermined threshold, and generate the control signal indicating a new level of the output current that is reduced from the first level. A method of controlling…
Output driver having output impedance adaptable to supply voltage and method of use
Granted: August 16, 2016
Patent Number:
9419588
An output driver is provided that adapts an output impedance of the output driver to the voltage level of a power supply, thereby providing a constant output impedance over a range of different operating voltages. The output driver includes a plurality of individual driver circuits, each one of the plurality of individual driver circuits configured to provide a plurality of predetermined output impedances in response to a plurality of power supply voltage level inputs and a decoder. The…
Low voltage differential signaling (LVDS) driver with differential output signal amplitude regulation
Granted: August 2, 2016
Patent Number:
9407268
An low voltage differential signaling (LVDS) driver is provide having an output voltage amplitude regulator for regulating an output voltage amplitude of the LVDS driver by receiving a differential output signal from a switched-polarity current generator of the LVDS driver at an output voltage amplitude regulator of the LVDS driver, detecting an output voltage amplitude of the differential output signal, comparing the output voltage amplitude to a reference voltage at the output voltage…
Packaged integrated circuits having high-Q inductors therein and methods of forming same
Granted: July 19, 2016
Patent Number:
9397151
A packaged integrated circuit includes an integrated circuit substrate and a cap bonded to a surface of the integrated circuit substrate. The cap has a recess therein that is at least partially lined with at least one segment of an inductor. This inductor may be electrically coupled to an electrical component within the integrated circuit substrate. In some embodiments, the inductor is patterned to extend along a sidewall and interior top surface of the recess, which extends opposite the…
