Multi-bit cell attenuator
Granted: June 21, 2016
Patent Number:
9374078
Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent…
Dual-coupled phase-locked loops for clock and packet-based synchronization
Granted: June 14, 2016
Patent Number:
9369270
A Synchronous Ethernet (SyncE) network device includes a pair of phase-locked loops including a first phase-locked loop responsive to a SyncE input clock and a second phase-locked loop coupled to the first phase-locked loop. The second phase-locked loop is configured to be simultaneously lockable to both the SyncE input clock via the first phase-locked loop and an IEEE 1588 packet stream, during a locked mode of operation, and also lockable to the SyncE input clock during a holdover mode…
Method and apparatus for efficient baseband unit processing in a communication system
Granted: June 14, 2016
Patent Number:
9369149
The method and apparatus of the present invention provides for reduced power consumption and cost while supporting wide bandwidth signals from a large number of antennas, as is required by next generation systems. In accordance with the present invention, a method and apparatus are provided for processing data in a baseband unit in which compressed signals from remote radio units are sent directly to the switch instead of to a separate conversion device. Thereby, the local input and…
Fractional reference-injection PLL
Granted: June 14, 2016
Patent Number:
9369139
Methods and apparatuses are described to reduce phase noise in a low noise fractional reference-injection phase locked loop (FRIPLL). The FRIPLL includes a ring voltage controlled oscillator (VCO). An output of the ring VCO is input to a fractional interpolative frequency divider (FIFD). A signal comparison circuit receives a reference clock signal and a further delayed output of the FIFD. The signal comparison circuit produces a control voltage signal in response to a phase difference…
Low-spurious fractional N-frequency divider and method of use
Granted: June 7, 2016
Patent Number:
9362928
A fractional N-frequency divider having a reduced fractional spurious output signal, which utilizes a multi-modulus frequency divider and an accumulator to generate a calibration-timing window that is used to calibrate two oscillator circuits and a phase compensation circuit. The calibrated phase compensation circuit is then used to mitigate the fractional spurs in the output signal of the fractional N-frequency divider. The fractional N-frequency divider may be implemented into a…
Method and apparatus for fast frequency acquisition in PLL system
Granted: June 7, 2016
Patent Number:
9362924
A Method and Apparatus for Fast Frequency Acquisition in PLL System has been disclosed. In one implementation a time to digital converter is used with cycle slip detection for fast acquisition and lock. In one implementation cycle slip detection is applied to determine if a feedback clock from an oscillator is faster than a reference clock or not in one measurement cycle.
System and method for voltage regulation of one-time-programmable (OTP) memory programming voltage
Granted: May 10, 2016
Patent Number:
9336896
An integrated circuit is provided that allows for the use of the same supply voltage pin to receive both a normal operating voltage for the integrated circuit (IC) and a one-time-programmable (OTP) memory program voltage sufficient to program an OTP memory located on the integrated circuit. In one embodiment, when an OTP programming voltage is received at a supply voltage pin of the IC, the OTP programming voltage is provided to the OTP memory of the integrated circuit and the OTP…
Flip chip bump array with superior signal performance
Granted: May 3, 2016
Patent Number:
9332629
An integrated circuit (342) that is electrically connected to a printed circuit board (246) with a package substrate (344) includes a circuit body (352), and a bump array (354) that electrically connects the circuit body (352) to the package substrate (244). The bump array (354) includes a first bump set (356) having a plurality of signal bumps (364) and a plurality of non-signal bumps (366) alternatingly interspersed and aligned along an axis. With the present design, the bump array…
Methods and apparatuses for a unified compression framework of baseband signals
Granted: April 12, 2016
Patent Number:
9313300
A method and apparatus provides a parameter estimation processor configured to estimate parameters used to compress data for transmission over a serial data link. The parameter estimation processor includes a processor. The processor includes user programmable inputs. The user programmable inputs set an input data packet length, a target compression ratio, and a resampling factor and allow filter parameters to be set. Input data information is received from an input data buffer of a data…
Integrated circuit device substrates having packaged crystal resonators thereon
Granted: April 5, 2016
Patent Number:
9306537
An integrated circuit device includes an integrated circuit substrate having a two piece package thereon. The package has a hermetically sealed cavity therein and a crystal resonator within the cavity. The crystal resonator includes at least one electrode electrically coupled to a portion of the integrated circuit substrate by an electrically conductive via, which extends at least partially through the package. The package may include a material selected from a group consisting of glass…
Digital extraction and correction of the linearity of a residue amplifier in a pipeline ADC
Granted: March 8, 2016
Patent Number:
9281831
Embodiments of a pipeline analog-to-digital converter is provided. In accordance with some embodiments, a pipeline analog-to-digital converter includes a stage, the stage including a residue amplifier that amplifies a residual voltage generated by the stage to obtain an amplified residual voltage; a backend digitizer that digitizes the amplified residual voltage to generate a digitized residual; and a digital correction circuit that corrects the digitized residual according to which zone…
Half-integer frequency dividers that support 50% duty cycle signal generation
Granted: February 23, 2016
Patent Number:
9270280
A fractional-N frequency divider includes a half-integer frequency divider and a duty cycle adjustment circuit. The half-integer frequency divider includes a multi-modulus divider containing a cascaded chain of div2/3 cells, which is responsive to a multi-bit modulus control signal, and a phase control circuit configured support half-integer frequency division by the multi-modulus divider, by providing an input terminal of the multi-modulus divider with a periodically phase-flipped input…
Process compensated delay
Granted: February 16, 2016
Patent Number:
9264027
A Process Compensated Delay has been disclosed. In one implementation delay is primarily based on electron mobility.
Method and apparatus for reduction of communications media energy consumption
Granted: January 19, 2016
Patent Number:
9240892
A Method and Apparatus for Reduction of Communications Media Energy Consumption have been disclosed. Media energy consumption can be reduced by mapping a periodic data pattern in data to an alternate data pattern that consumes less energy when the alternate pattern is transmitted on the communications media in place of the original data pattern. The detection of the original selected patterns and the choice of replacement patterns may be made automatically or according to the…
Compression of baseband signals in base transceiver system processors
Granted: January 19, 2016
Patent Number:
9240803
A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses baseband signal samples resulting from analog to digital conversion of a received analog signal followed by digital downconversion. The compressed signal samples are transferred over the serial data link to the baseband processor then…
Monolithic clock generator and timing/frequency reference
Granted: January 19, 2016
Patent Number:
9240792
A periodic signal generator includes a resonant LC tank circuit that generates a periodic reference signal at a first frequency at a differential output thereof. A temperature-responsive frequency compensation module is electrically coupled to the differential output of the resonant LC tank circuit. This module includes a temperature dependent voltage control module that generates a temperature dependent control voltage and an array of switchable capacitive modules that is electrically…
Methods of packet-based synchronization in non-stationary network environments
Granted: January 12, 2016
Patent Number:
9236967
Methods of packet-based synchronization in non-stationary network environments can include accumulating timestamps transmitted in packets between master and slave devices that are separated from each other by a packet network. Operations are also performed to determine whether first timestamps accumulated in a first direction across the packet network demonstrate that a first packet delay variation (PDV) sequence observed from the first timestamps is stationary. Thereafter, estimates of…
Fractional divider based phase locked loops with digital noise cancellation
Granted: January 12, 2016
Patent Number:
9236873
A PLL includes a fractional divider to generate a periodic PLL output signal in response to REFHF. The fractional divider includes a digital control circuit (DDC) responsive to a digital control input signal and a multi-modulus divider (MMD), which is responsive to REFHF and a first digital control output signal generated by the DDC. A feedback divider (FD) is provided to generate a FD output signal in response to an MMD output signal generated by the MMD. A phase detector (PD) is…
Digital filter for phase-locked loop integrated circuits
Granted: January 12, 2016
Patent Number:
9236871
A digital filter for a frequency synthesizer (e.g., PLL, UFT) may include an analog-to-digital (ADC) converter, which is responsive to a control voltage at an input thereof, and a digital-to-analog (DAC) converter, which has an input responsive to a signal generated at an output of the ADC. An impedance element is provided between the DAC and ADC. The impedance element has real and reactive components, a first current carrying terminal electrically coupled to an output of the DAC and a…
Method and apparatus for efficient radio unit processing in a communication system
Granted: December 15, 2015
Patent Number:
9215296
The method and apparatus of the present invention provides for reduced power consumption and cost while supporting wide bandwidth signals from a large number of antennas, as is required by next generation systems. In accordance with the present invention, a method and apparatus are provided for processing data in a radio unit of a communication system by receiving compressed data at one or more interfaces or internal resources of a distributed switch of a radio unit, operating the…
