Integrated Device Tech Patent Grants

Method and apparatus for efficient data compression in a communication system

Granted: December 1, 2015
Patent Number: 9203933
A method and apparatus that compresses signal data to generate compressed signal data having a low latency jitter while maintaining an acceptable compression ratio and reasonable degradation, as is required by next generation systems. A method and apparatus for compressing data in a communication system by receiving uncompressed data at a compressor of the communication system, analyzing the uncompressed data at the compressor to estimate at least one compression parameter to be applied…

Method and apparatus for congestion and fault management with time-to-live

Granted: December 1, 2015
Patent Number: 9203769
A method and apparatus for congestion and fault management with time-to-live (TTL) have been disclosed. Each time a packet is transferred into an Egress Port's Final Buffer, an associated TTL Timeout Counter will be loaded with a value. If the packet cannot be transferred out of the Egress Port before TTL timeout, it will be purged by removing a memory buffer pointer from the corresponding Virtual Output Queue (VOQ) entry.

Self-adaptive current-mode-control circuit for a switching regulator

Granted: November 10, 2015
Patent Number: 9184659
A current-mode-control circuit for a switching regulator is provided. The circuit includes a first transistor coupled to a power supply voltage, a second transistor, and an inductor. The circuit further includes a slope compensation generation circuit coupled to the output of the current control circuit through a feedback loop, the slope compensation generation circuit generating a slope compensation current related to the output voltage, an inductor current sensing circuit coupled to…

Systems and methods for peak detection in automatic gain control circuits in high-speed wireline communications

Granted: October 20, 2015
Patent Number: 9166835
Methods and systems for peak detection as part of automatic gain control in high-speed communications are provided. A peak detection system uses a portion of an input signal to generate a reference signal for comparison with the input signal. The comparison produces a differential error signal that is in turn used to produce one or more full swing pulses based on the comparison. A pulse counter counts the pulses, and if the count in a single clock cycle is above a determined threshold, a…

Systems and methods for estimation of offset and gain errors in a time-interleaved analog-to-digital converter

Granted: October 6, 2015
Patent Number: 9154147
The present disclosure relates to the field of background estimation in a time-interleaved analog-to-digital converter (ADC). More specifically, the present disclosure relates to systems and methods for background estimation of offset and gain errors in a time-interleaved ADC based on sample count. The error estimation unit of the time-interleaved ADC system includes a counting unit, a subtractor and an integrator. The method for estimating an offset error in a time-interleaved ADC…

Apparatuses, systems, and methods for a monotonic transfer function in wireless power transfer systems

Granted: September 29, 2015
Patent Number: 9148024
A wireless power-transfer system includes a power-transmitting device and a power-receiving device. A frequency generator generates a power-transmit frequency to stimulate transmit coil and transmit resonance adjuster, which generate a near-field electromagnetic radiation at an adjustable coupling frequency. The power-receiving device includes a receive coil and a receive resonance adjuster for receiving the near-field electromagnetic radiation when the receive coil is within a coupling…

Method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe bridges

Granted: September 22, 2015
Patent Number: 9143346
A method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges have been described. A single level enqueue method with dynamic buffering and dequeuing based on packet re-ordering is disclosed. Single level packet routing and scheduling to meet SRIO and PCIe rules to enqueue packets based on FType/TType is disclosed. Backpressure based on ingress watermarks for different packet types is…

Apparatuses and system and method for auto-configuration of a power control system

Granted: September 15, 2015
Patent Number: 9136764
Power control systems and power control devices may include a power control chip having a power control module configured to generate a power stage control signal, and an external power stage having a timing control module. The timing control module may be configured to receive the power stage control signal and generate a timing control signal controlling at least one switch to regulate an output voltage of the external power stage. The power control device further includes an…

Protection for analog to digital converters

Granted: September 1, 2015
Patent Number: 9124286
Systems and methods for protecting an analog-to-digital converter (ADC) are provided. The provided systems and methods utilize comparators in a circuit of a stage of the ADC to compare a reference signal to an input signal and output one or more maximum signals when the input signal exceeds the reference signal. A decoder in the stage of the ADC may output a reset signal to another circuit in the stage of the ADC when a predetermined number of the maximum signals are received. When the…

Self-adaptive multi-modulus dividers containing div2/3 cells therein

Granted: August 25, 2015
Patent Number: 9118333
Integrated circuit devices include programmable dividers, such as fractional-N dividers, which can utilize multi-modulus dividers (MMD) therein. A multi-modulus divider includes a cascaded chain of div2/3 cells configured to support a chain length control operation that precludes generation of an intermediate divisor in response to a change in value of a chain length control byte P<n:0> during an update time interval and may even fully turn off one or more of the div2/3 cells not…

Systems and methods for adaptive equalization control for high-speed wireline communications

Granted: August 25, 2015
Patent Number: 9118295
Methods and systems for conditioning wireline communications to remove intersymbol interference are provided that used adaptive equalization. The method and systems include using a digital finite state machine to control two feedback loops that adjust the gain and power of the input signal relative to a supplied reference. The eye height of the input signal is conditioned by a gain feedback loop so that signal equalization can be performed in a known state. The digital finite state…

Apparatuses and system having separate power control and timing control of a power control system and related method

Granted: August 18, 2015
Patent Number: 9112410
Power control systems and power control devices may include a power control chip having a power control module configured to generate a power stage control signal, and at least one power stage having a timing control module that is physically separate from the power control module. The timing control module may be configured to receive the power stage control signal and generate a timing control signal controlling at least one switch to regulate an output voltage of the at least one…

Power management integrated circuit using a flexible script-based configurator and method for power management

Granted: July 28, 2015
Patent Number: 9092217
A power management integrated circuit incorporates (a) a microprocessor; (b) a non-volatile memory accessible by the microprocessor for storing programs executable by the microprocessor; (c) a random access memory accessible by the microprocessor; (d) an external interface which allows an external device to communicate with the power management integrated circuit; and (e) power regulators providing regulated output voltages from the power management integrated circuit, each power…

Microelectromechanical resonators having offset [100] and [110] crystal orientations

Granted: July 28, 2015
Patent Number: 9090451
A TPoS resonator includes a substrate and a resonator body suspended over the substrate by at least a first pair of fixed supports (e.g., tethers) that attach to first and second ends of the resonator body. The resonator body includes monocrystalline silicon, which has a [100] crystallographic orientation that is offset by ±? degrees relative to a nodal line of the resonator body (e.g., tether-to-tether axis) when the resonator body is operating at a resonant frequency, where a is a…

Clock generation circuits using jitter attenuation control circuits with dynamic range shifting

Granted: June 23, 2015
Patent Number: 9065459
An apparatus includes a phase locked loop (PLL) circuit configured to generate a PLL output signal from an oscillator signal and a control circuit configured to generate a measure of a difference between the PLL output signal and an input clock signal at a control output thereof. The apparatus further includes a dynamic range shifter circuit coupling the control output of the control circuit to a control input (e.g., a feedback divider control input) of the PLL circuit and configured to…

Frequency domain compression in a base transceiver system

Granted: June 16, 2015
Patent Number: 9059778
A method and apparatus provide signal compression for transfer over serial data links in a base transceiver system (BTS) of a wireless communication network. For the uplink, an RF unit of the BTS applies frequency domain compression of baseband signal samples, resulting from analog to digital conversion of received analog signals followed by digital downconversion, forming compressed coefficients. After transfer over the serial data link, the baseband processor then applies frequency…

Transmission of multiprotocol data in a distributed antenna system

Granted: June 9, 2015
Patent Number: 9055472
In a distributed antenna system (DAS) and a local area network (LAN), a common communication infrastructure distributes data from radio-based and Internet-based sources. A radio equipment (RE) of the DAS interfaces to a LAN segment. For the downlink, a gateway maps radio signal data from a radio equipment controller (REC) and data packets from a switch to mixed-data frames using a radio data interface protocol for transmission in the DAS. At the RE, the signal data and data packets are…

Packaged MEMS-based oscillator circuits that support frequency margining and methods of operating same

Granted: April 7, 2015
Patent Number: 9000853
Integrated circuit devices include a packaged MEMS-based oscillator circuit, which is configured to support bidirectional frequency margining of a periodic output signal. This bidirectional frequency margining is achieved using a first signal to synchronize changes in a frequency of the periodic output signal and a second signal to control whether the changes in the frequency of the periodic output signal are incremental or decremental. In particular, the oscillator circuit may be…

OFDM signal processing in a base transceiver system

Granted: March 24, 2015
Patent Number: 8989088
A method and apparatus provides OFDM signal compression for transfer over serial data links in a base transceiver system (BTS) of a wireless communication network. For the uplink, an RF unit of the BTS applies OFDM cyclic prefix removal and OFDM frequency transformation of the baseband signal samples followed by frequency domain compression of the baseband signal samples, resulting from analog to digital conversion of received analog signals followed by digital downconversion, forming…

Method and apparatus for providing near-zero jitter real-time compression in a communication system

Granted: March 24, 2015
Patent Number: 8989257
The method and apparatus of the present invention provides for the compression of signal data having a low latency jitter while maintaining a target compression ratio and reasonable degradation, as is required by next generation systems. In accordance with the present invention, a method and apparatus are provided for compressing data in a communication system by receiving uncompressed packet at a compressor of the communication system, segmenting the packet into a plurality of packet…