Packet switch with enqueue structure for odering packets
Granted: October 9, 2012
Patent Number:
8284790
A packet switch receives packets at an ingress port, generates enqueue records for the packets, and stores the enqueue records in an enqueue structure. The enqueue record of a packet includes a pass flag for indicating whether a permissive passing rule is applicable to the packet. The packet switch determines a routing order for the packets stored in the ingress port based on the enqueue records and a set of ordering rules including the permissive passing rule. If a packet is blocked in…
Push-pull spread spectrum clock signal generator
Granted: October 9, 2012
Patent Number:
8284816
A spread spectrum clock signal generator modulates a reference clock signal based on a spread spectrum frequency profile and includes a phase-lock loop for generating a spread spectrum clock signal by aligning a phase of the modulated reference clock signal with a phase of the spread spectrum clock signal. The spread spectrum clock signal generator also includes a loop modulator for modulating the spread spectrum clock signal based on the spread spectrum frequency profile. Because the…
Flash analog-to-digital converter
Granted: October 9, 2012
Patent Number:
8284091
An analog-to-digital converter comprises a signal input (6) for receiving an analog input signal and a set of comparators (4). Each comparator (4) has a first input (21) connected to the signal input (6) and a second input (22) connected to a reference voltage (16). Each comparator generates an output based on the comparison of the signals at the first input (21) and second input (22). The reference voltage is the same for all comparators. The set of comparators (4) has a non-identical…
Switch for use in a programmable gain amplifier
Granted: October 2, 2012
Patent Number:
8279007
A switch circuit is provided. The switch circuit may include a first transistor having a source terminal to accept an input signal, a drain terminal to provide an output signal, and a gate; a power supply providing a gate voltage. The switch circuit may also include a circuit to couple a switch signal to the gate, wherein the circuit turns the first transistor ‘off’ for all values of the input signal when the switch signal is ‘low.’ A programmable gain amplifier (PGA) is also…
Method and apparatus for fast PLL initialization
Granted: September 11, 2012
Patent Number:
8265219
A method and apparatus for fast PLL initialization have been disclosed where control of a VCO is based on a selected control signal which is based upon either a comparison signal or a prespecified signal.
Method of processing signal data with corrected clock phase offset
Granted: September 4, 2012
Patent Number:
8259888
The present invention provides a method of processing signal data comprising generating a first clock signal and a second clock signal and processing the signal data using the first clock signal and the second clock signal. While processing the signal data, the phase difference between the first clock signal and the second clock signal is measured and corrected for so that a target phase difference between the first clock signal and the second clock signal is maintained.
Method and apparatus for adaptive buffer management for traffic optimization on switches
Granted: August 28, 2012
Patent Number:
8254399
A method and apparatus for adaptive buffer management for traffic optimization on switches have been disclosed where pattern injection and traffic monitoring with forced congestion allows optimizing buffers while accounting for actual system delays.
Method for measuring phase locked loop bandwidth parameters for high-speed serial links
Granted: August 28, 2012
Patent Number:
8254515
A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator; determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock…
Packets transfer device having data absorbing buffers with elastic buffer capacities
Granted: August 28, 2012
Patent Number:
8255599
In PCI-Express and alike communications systems, data bandwidth per channel can vary as a result of negotiated port bifurcation during network bring-up. Disclosed are systems and methods for adjusting FIFO depths in response to negotiated bandwidth per channel so that data absorbing FIFO's of respective channels are not arbitrarily too deep or too shallow relative to the data bandwidths of the channels the FIFO's serve.
Multi-touch touch screen with single-layer ITO bars arranged in parallel
Granted: August 21, 2012
Patent Number:
8248383
A touch screen includes a plurality of single-layer ITO bars having a substantially rectangular shape and arranged in parallel to each other in order to detect touches on the touch screen. The location of a touch on the touch screen in the direction along an ITO bar is determined by applying a signal on one end of the ITO bar and measuring the change in the amplitude and the delay of the signal on the opposite end of the ITO bar. Such application and measurement of the signal can be…
Apparatuses and methods for a SCR-based clamped electrostatic discharge protection device
Granted: August 21, 2012
Patent Number:
8248741
A SCR-based based electrostatic discharge protection device with a shunt path is provided. The shunt path operates at a low resistance when an enabling signal of the shunt path is asserted and a high resistance when the enabling signal is negated. The shunt path connects the cathode and the gate of the silicon-controlled rectifier, and provides a conductive path for displacement current from a parasitic capacitance when the shunt path is enabled, such as when power is provided to the…
Circuit including current-mode logic driver with multi-rate programmable pre-emphasis delay element
Granted: August 21, 2012
Patent Number:
8248135
A circuit (10) includes a circuit input (12), a circuit output (16) and a one or more delay elements (22) positioned between the circuit input (12) and the circuit output (16). The delay elements (22) each include a differential input pair (234), a latch stage (236) and a delay controller (244A1, 244A2, 244B1, 244B2). The delay controller (244A1, 244A2, 244B1, 244B2) selectively apportions current between the differential input pair (234) and the latch stage (236) to achieve a desired…
System having capability for daisy-chained serial distribution of video display data
Granted: August 7, 2012
Patent Number:
8237624
A serial display interface such as the VESA-Display Port interface is expanded to support daisy chained coupling of one display monitor to the next. Each daisy chain wise connectable display monitor has a local daisy chain transceiver device associated with it where the local transceiver device selectively picks off passing through video data streams in response to embedded MDID identification signals and forwards the selectively picked off data to the local monitor. The local…
Method and apparatus for selective packet discard
Granted: August 7, 2012
Patent Number:
8238339
A method and apparatus for selective packet discard have been disclosed where two bits are added to a packet to indicate various discard options.
Audio system with tone controller for use in a computer
Granted: August 7, 2012
Patent Number:
8238577
A computer audio system includes an audio codec and a lone controller. The audio codec is operably coupled to receive audio information, which includes tone control settings, PCM digital audio inputs and PCM digital audio outputs. In addition, the audio codec may receive audio information as analog input signals via a line-in, a CD input, or an auxiliary input. Based on the audio information, the audio codec provides a first stereo output, a second stereo output and a monotone audio…
Audio codec producing a tone controlled output
Granted: July 31, 2012
Patent Number:
8233639
An audio codec includes an input for receiving audio information. Audio processing circuitry produces a first stereo audio signal, a second stereo audio signal, and a monotone audio signal based on the audio information. A low pass filter filters the monotone audio output, wherein the low pass filter passes a bass component of the monotone audio signal substantially unattenuated and attenuates higher frequency components of the monotone audio signal. A high pass filter filters the first…
Efficient strip-down and re-alignment of ingressing physical layer/data layer packets in an aggregated PCI-express port having eight lanes
Granted: July 31, 2012
Patent Number:
8234424
In PCI-Express and alike communications systems, number of lanes used per channel or port can vary as a result of negotiated lane aggregation during network bring-up. Disclosed are systems and methods for efficiently realigning packet data and stripping out control bytes in a by-eight port configuration as the packet data ingresses from the physical layer (PL), past the data link layer (DL) and into the transaction layer (TL). It is shown that data routing can be reduced to just two,…
Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory system
Granted: July 24, 2012
Patent Number:
8230174
A multi-queue FIFO memory device that uses existing pins of the device to load a desired number of queues (N) into a queue number register is provided. The queue number register is coupled to a queue size look-up table (LUT), which provides a queue size value in response to the contents of the queue number register. The queue size value indicates the amount of memory (e.g., the number of memory blocks) to be included in each of the N queues. The queue size value is provided to a queue…
Method and circuit for DisplayPort video clock recovery
Granted: July 10, 2012
Patent Number:
8217689
A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device,…
Methods and apparatuses for clock domain crossing
Granted: July 3, 2012
Patent Number:
8212594
Clock-domain-crossing systems and methods include an integrator that accumulates input samples over multiple clock cycles in a first clock domain to generate an accumulation result. Clock-domain-crossing circuitry samples the accumulation result in the first clock domain after each of a repeating accumulation count to generate a first domain accumulation. The first domain accumulation is sampled in a second clock domain after a time delay to generate a second domain accumulation. The…
