Thin-film bulk acoustic resonators having multi-axis acoustic wave propagation therein
Granted: February 5, 2013
Patent Number:
8368487
Microelectromechanical resonators include a resonator body anchored to a surrounding substrate by at least one support that holds the resonator body opposite a recess in the substrate. The resonator body has first and second pluralities of interdigitated drive and sense electrodes thereon. The first plurality of interdigitated drive and second electrodes are aligned to a first axis of acoustic wave propagation in the resonator body when the resonator body is operating at resonance. In…
Switched-capacitor pipeline ADC stage
Granted: January 29, 2013
Patent Number:
8362939
A switched capacitor pipeline ADC stage is disclosed, in which a reset switch is included to reset the sampling capacitor during a first part of the sampling period. The reset switch thereby removes history and makes the sampling essentially independent of previous samples taken, thus reducing inter symbol interference (IS) and distortion resulting therefrom, without significantly affecting the sampling period or power usage of the device.
Accurate resistance capacitance (RC) time constant calibration with metal-oxide-metal (MOM) capacitors for precision frequency response of integrated filters
Granted: January 29, 2013
Patent Number:
8364433
A calibration system employed for use with a resistance capacitance (RC) filter having resistors and capacitors with parasitic capacitance associated therewith. The calibration system has a digital calibration circuit receiving a time constant signal and generating, based thereon, a control word of N digital bits. The calibration system includes an analog monitor circuit having monitor capacitance assembly having a particular equivalent resistor and capacitor configuration. The analog…
AD converter
Granted: January 8, 2013
Patent Number:
8350743
Analog to digital conversion is performed by sampling an input voltage followed by AD conversion of the sampled voltage. In the sample and hold circuit a differential amplifier output voltage is generated between the first and second output of a differential amplifier in response to the sampled input voltage. A conversion polarity is selected by connecting the one output or the other of the differential amplifier to a circuit node in an AD conversion circuit using a first or second…
Compression of baseband signals in base transceiver system radio units
Granted: December 11, 2012
Patent Number:
8331461
A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses baseband signal samples resulting from analog to digital conversion of a received analog signal followed by digital downconversion. The compressed signal samples are transferred over the serial data link to the baseband processor then…
Method and apparatus for duty-cycle correction with reduced current consumption
Granted: December 4, 2012
Patent Number:
8324948
A method and apparatus for duty-cycle correction with reduced current consumption have been described.
Method and apparatus for dynamic traffic management with packet classification
Granted: December 4, 2012
Patent Number:
8325723
A method and apparatus for dynamic traffic management with packet classification have been disclosed where packet size, variation, and count may be used to select credit or packet based arbitration.
System and method for generating locator polynomials
Granted: December 4, 2012
Patent Number:
8327243
A syndrome generator generates odd syndromes of a sequence of syndromes and stores the odd syndromes in registers. A syndrome sequencer identifies the register storing the next syndrome of the sequence of syndromes, reads the syndrome from the register, and outputs the syndrome to a sequential polynomial generator. Further, the syndrome sequencer generates an even syndrome by squaring the syndrome read from the register and writes the even syndrome into the same register. Moreover, the…
Compression of baseband signals in base transceiver system interfaces
Granted: November 27, 2012
Patent Number:
8320433
A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses baseband signal samples resulting from analog to digital conversion of a received analog signal followed by digital downconversion. The compressed signal samples are transferred over the serial data link to the baseband processor then…
Method and apparatus for programmable buffer with dynamic allocation to optimize system throughput with deadlock avoidance on switches
Granted: November 27, 2012
Patent Number:
8320392
A method and apparatus for programmable buffer with dynamic allocation to optimize system throughput with deadlock avoidance on switches have been disclosed where a buffer availability is based on a programmable reservation size for dynamic allocation.
Apparatuses and methods for a voltage level shifting
Granted: November 27, 2012
Patent Number:
8319540
Level shifting circuits and a related method are disclosed herein. An embodiment of the present invention includes a voltage level shifter, comprising a first pull up transistor coupled to a high voltage signal and a first pull down transistor coupled between the first pull up transistor and a low voltage signal and controlled by an input signal. The voltage level shifter further includes a first bias transistor serially coupled between the first pull up transistor and the first bias…
Method and apparatus for fail-safe start-up circuit for subthreshold current sources
Granted: November 20, 2012
Patent Number:
8316245
A method and apparatus for fail-safe start-up circuit for subthreshold current sources have been disclosed.
Protocol translation in a serial buffer
Granted: November 13, 2012
Patent Number:
8312190
A serial buffer includes a first port configured to operate in accordance with a first serial protocol and a second port configured to operate in accordance with a second serial protocol. A first translation circuit of the serial buffer allows packets received on the first port to be translated to the second serial protocol, and then transferred to the second port. A second translation circuit of the serial buffer allows packets received on the second port to be translated to the first…
Serial buffer to support request packets with out of order response packets
Granted: November 13, 2012
Patent Number:
8312241
Within a serial buffer, request packets are written to available memory blocks of a memory buffer, which are identified by a free buffer pointer list. When a request packet is written to a memory block, the memory block is removed from the free buffer pointer list, and added to a used buffer pointer list. Memory blocks in the used buffer pointer list are read, thereby transmitting the associated request packets from the serial buffer. When a request packet is read from a memory block,…
Lead frame package
Granted: October 23, 2012
Patent Number:
8294249
A lead frame package is disclosed where transmission signals are coupled into a die from a pair of lead frames through bonding wires that are separated by no more than three times a diameter of one of the bonding wires. In some embodiments, pairs of lead frames carrying differential transmission signals can be shielded by adjacent pairs of ground and power leads that are coupled into the die through bonding wires that are also separated by no more than three times a diameter of one of…
Predictive flow control for a packet switch
Granted: October 23, 2012
Patent Number:
8295293
A packet switch issues credits to a link partner based on credit values and updates the credit values to indicate credits consumed by the link partner based on packets received from the link partner by the ingress port. Additionally, the packet switch selects credit threshold values corresponding to a transmission period of imminent credit starvation of the link partner and compares the updated credit values with the credit threshold values. The packet switch issues additional credits to…
Technique to reduce clock recovery amplitude modulation in high-speed serial transceiver
Granted: October 16, 2012
Patent Number:
8289061
A method is provided for improving clock recovery signal jitter in digital communication based on a phase adjustment technique in a phase interpolation. A clock signal is expressed as the combination of two sinusoidal signals. The phase interpolating process determines the amplitude of the first sinusoidal signal, and the amplitude of the second sinusoidal signal that is 90° out of phase from the first sinusoidal signal. The clock signal is then formed by combining first sinusoidal…
System and method for arbitration using availability signals
Granted: October 16, 2012
Patent Number:
8289989
A packet switch includes an arbiter that generates an availability signal indicating whether one or more pseudo-ports are available for receiving data. Each pseudo-port identifies one or more output ports of the packet switch. An input port of the packet switch receives data of a data packet, generates a grant request identifying a pseudo-port, and issues the grant request to a grant request filter. The grant request filter determines based on the availability signal whether the grant…
Methods of forming microdevice substrates using double-sided alignment techniques
Granted: October 9, 2012
Patent Number:
8283256
Methods of forming substrates having two-sided microstructures therein include selectively etching a first surface of the substrate to define a plurality of alignment keys therein that extend through the substrate to a second surface thereof. A direct photolithographic alignment step is then performed on a second surface of the substrate by aligning a photolithography mask to the plurality of alignment keys at the second surface. This direct alignment step is performed during steps to…
Flash analog-to-digital converter
Granted: October 9, 2012
Patent Number:
8284091
An analog-to-digital converter comprises a signal input (6) for receiving an analog input signal and a set of comparators (4). Each comparator (4) has a first input (21) connected to the signal input (6) and a second input (22) connected to a reference voltage (16). Each comparator generates an output based on the comparison of the signals at the first input (21) and second input (22). The reference voltage is the same for all comparators. The set of comparators (4) has a non-identical…
