Distributed transceiver signal switching circuit
Granted: January 28, 2020
Patent Number:
10547120
An apparatus includes a package and a chip. The package may comprise (i) a plurality of bonding pads, (ii) a plurality of combiner/splitter circuits, and (iii) a plurality of bumps. The bonding pads may be configured to electrically connect the package with a printed circuit board substrate. The combiner/splitter circuits generally connect each of the bonding pads to two respective bumps of the plurality of bumps. The chip is generally disposed in the package. The chip may comprise a…
Transmit-receive switch with integrated power detection
Granted: January 14, 2020
Patent Number:
10536186
An apparatus includes a plurality of impedance matching networks, a common port, a first switch circuit and a second switch circuit. The impedance matching networks may be (i) connected in series between an input port and an output port and (ii) configured to generate a power detection signal in response to a radio-frequency signal. The radio-frequency signal may be a transmit signal or a receive signal. The common port may be (i) connected to the impedance matching networks and (ii)…
Use of ring oscillators for multi-stop time measurements
Granted: January 14, 2020
Patent Number:
10534322
A multi-stop time-to-digital converter (TDC, 110) includes single-stop TDCs (510) connected to output nodes of a ring oscillator (504). Other features and embodiments are also provided.
Battery management integrated circuit
Granted: December 31, 2019
Patent Number:
10523041
In accordance with aspects of the present invention, a wireless power integrated circuit is presented. The wireless power integrated circuit includes a wireless power receiver circuit; a battery charger circuit; and a microprocessor coupled to control the wireless power receiver and the battery charger circuit.
Transceiver resonant receive switch
Granted: December 17, 2019
Patent Number:
10511344
An apparatus comprises an input port, an output port, and a resonant receive switch circuit. The resonant receive switch circuit may be coupled between the input port and the output port. The resonant receive switch circuit may comprise a first switch, a second switch, and an input matching circuit. When the first and the second switches are in a non-conducting state, a signal at the input port is passed to the output port. When the first and the second switches are in a conducting…
Wireless power transmitter having low noise and high efficiency, and related methods
Granted: December 17, 2019
Patent Number:
10511222
A wireless power transmitter comprises a bridge inverter including a first switch and a second switch coupled together with a first switching node therebetween, and a first capacitor coupled to the first switching node. The transmitter further includes control logic configured to control the first switch and the second switch according to an operating frequency to generate an AC power signal from a DC power signal, and a resonant tank operably coupled to the first switching node of the…
Wide programmable gain receiver data path for single-ended memory interface application
Granted: December 3, 2019
Patent Number:
10496587
An apparatus includes an interface and a plurality of impedance branches. The interface may be configured to receive a data signal and a plurality of selection signals. The plurality of impedance branches may comprise a group of branches and a separated branch. The plurality of impedance branches may be configured to adjust an impedance value and a gain of a data path for the data signal in response to the selection signals. The group of branches may be controlled in response to the…
Frequency synthesizer with tunable accuracy
Granted: November 19, 2019
Patent Number:
10483982
An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first code by counting a number of cycles of an input clock signal during a period. The period may be determined by an output clock signal and a second code. The second circuit may be configured to generate a third code by a delta-sigma modulation of the first code. The third circuit may be configured to generate the output clock signal in response to the third…
Fast memory access control for phase and gain
Granted: November 19, 2019
Patent Number:
10483653
An apparatus includes a switching circuit and a plurality of registers. The switching circuit may be configured to generate a sequence of pulses in a plurality of control signals in response to a plurality of cycles of an enable signal. The registers may be hardwired as a plurality of subsets. Each of the subsets of the registers may be configured to (a) buffer a plurality of setting values received from a memory and (b) present the setting values from the registers to a plurality of…
Time slotted bus system for multiple coupled digital phase-locked loops
Granted: November 12, 2019
Patent Number:
10476509
An apparatus includes a plurality of digital phase-locked loops and a time slotted bus. The time slotted bus is configured to couple the plurality of digital phase-locked loops. The plurality of digital phase-locked loops may be configured to exchange parameters between two or more of the plurality of digital phase-locked loops using one or more time slots of the time slotted bus.
Low power delay buffer between equalizer and high sensitivity slicer
Granted: November 12, 2019
Patent Number:
10475506
An apparatus includes a continuous-time linear equalizer circuit, a buffer and at least one slicer. The continuous-time linear equalizer circuit may be configured to generate a first intermediate signal by equalizing an input signal relative to a reference voltage. The input signal may be single-ended. The first intermediate signal may be differential. The buffer may be configured to generate a second intermediate signal by delaying the first intermediate signal. The second intermediate…
Active twisted figure ‘8’ inductor
Granted: November 5, 2019
Patent Number:
10468179
An inductor is disclosed that includes an arrangement of lobes, each of the lobes in the arrangement of lobes including a generator, the arrangement of lobes interconnected such that, when currents are provided by each generator in the arrangement of lobes, each lobe in the arrangement of lobes produces a magnetic field with a defined polarity relative to the arrangement of lobes. When the arrangement of lobes are appropriately interconnected, the magnetic field from the arrangement of…
Long range beamforming and steering in wireless communication links
Granted: October 15, 2019
Patent Number:
10448263
An apparatus includes a transceiver circuit, an antenna and a focus array. The transceiver circuit may have a plurality of fed channels configured to generate a plurality of signals. The antenna may have a plurality of antenna arrays configured to generate one or more beams in response to the signals. Each antenna array may (i) have a plurality of subarrays and (ii) be coupled to the fed channels of the transceiver circuit. The focus array may have a plurality of focal zones configured…
Wireless powered digital lock
Granted: October 8, 2019
Patent Number:
10438431
An electronic lock that interacts with a mobile device is presented. In accordance with some embodiments, an electronic lock includes a wireless power receiver configured to receiver power from a mobile device; a processor coupled to receive power from the wireless power receiver; a memory coupled to the processor and to receive power from the wireless power receiver; a communication unit coupled to the processor and to receive power from the wireless power receiver, the communication…
Open loop solution in data buffer and RCD
Granted: October 8, 2019
Patent Number:
10437279
An apparatus includes a clock tree circuit, a first phase interpolator circuit and a second phase interpolator circuit. The clock tree circuit may be configured to generate a first clock delayed from a system clock by a constant time. The first phase interpolator circuit may be in a calibration loop and configured to generate a second clock with a programmable phase delay relative to the first clock. The programmable phase delay may be controlled by a control value. The calibration loop…
Method for time-dependent visual quality encoding for broadcast services
Granted: October 1, 2019
Patent Number:
10432931
A method for encoding a video signal generally includes enabling multiple encoding passes based on a first profile, generating an encoded bitstream during a first time period by encoding each of a plurality of images in the video signal with the multiple encoding passes in a circuit based on the first profile, disabling the multiple encoding passes based on a second profile and generating the encoded bitstream during a second time period by encoding each of the images using a single…
Auto-phase-shifting and dynamic on time control current balancing multi-phase constant on time buck converter
Granted: September 24, 2019
Patent Number:
10425093
An apparatus including a first circuit and a second circuit. The first circuit may generate an output signal with a regulated voltage and maintain a constant switch frequency having a first on time and a first off time. The second circuit may generate a shifted signal based on a phase delay with respect to the output signal and maintain a shifted frequency having a second on time and a second off time. The second on time may follow the first on time by the phase delay. The second on time…
Distributed transceiver signal switching circuit
Granted: September 17, 2019
Patent Number:
10418719
An apparatus include a package, a chip and a plurality of bumps. The package may include (i) a plurality of bonding pads configured to exchange a plurality of radio-frequency signals with an antenna panel and (ii) a plurality of transmission lines configured to exchange the radio-frequency signals with the bonding pads. Two of the transmission lines may be connected to each of the bonding pads. The chip may be disposed in the package and may include (i) a plurality of transceiver…
Open loop solution in data buffer and RCD
Granted: September 10, 2019
Patent Number:
10409320
An apparatus comprising an open loop circuit and a delay circuit. The open loop circuit may be configured to generate an in-phase clock signal by performing a phase alignment in response to (i) a clean version of a system clock and (ii) a delayed version of a strobe signal. The delay circuit may be configured to (i) generate the delayed version of the strobe signal in response to (a) the strobe signal received from a memory interface and (b) a delay amount received from a calibration…
RF amplifier linearity enhancement with dynamically adjusted variable load
Granted: September 3, 2019
Patent Number:
10404216
An apparatus comprises an amplifier having a predefined linear range and a shunt load. The shunt load may be connected to an output, an input, or between gain stages of the amplifier. An impedance of the shunt load dynamically varies in response to a level of a signal presented at a node formed by interconnection of the shunt load and the amplifier, extending linearity of the amplifier beyond the predefined range.
