Reduced VSWR switching
Granted: June 11, 2019
Patent Number:
10320381
Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more…
Frequency divider with selectable frequency and duty cycle
Granted: June 11, 2019
Patent Number:
10320376
A frequency divider system and method includes a split-divisor frequency divider module. The split-divisor frequency divider module receives a clock signal and generates an output signal based on a first divisor and a second divisor. The clock signal and output signal each have rectangular waveforms characterized by a respective frequency and pulse width. The frequency of the output signal is a selectable integer fraction of the frequency of the clock signal, the frequency of the output…
Multimode wireless power receivers and related methods
Granted: June 11, 2019
Patent Number:
10320234
A wireless power receiver comprises a resonant tank configured to generate an AC power signal responsive to an electromagnetic field, a rectifier configured to receive the AC power signal and generate a DC output power signal, and control logic configured to control the resonant tank to reconfigure and adjust its resonant frequency responsive to a determined transmitter type of a wireless power transmitter. The control logic may operate the wireless power receiver as a multimode receiver…
Methods and apparatuses for edge preserving and/or edge enhancing spatial filter
Granted: June 4, 2019
Patent Number:
10313565
A technique to perform edge-aware spatial noise filtering that may filter random noise from frames while maintaining the edges in the frames. The technique may include receiving a frame comprising a pint ht of pixels, filtering a subset of the plurality of pixels based on a weighting factor associated with each pixel of the subset of pixels, wherein the weighting factor is at least in part based on a difference in pixel value between the pixel and the individual pixels in the subset, and…
Hierarchical caching and analytics
Granted: June 4, 2019
Patent Number:
10313470
A system includes at least one end-node, at least one edge node, and an edge cloud video headend. The at least one end node generally implements a first stage of a multi-stage hierarchical analytics and caching technique. The at least one edge node generally implements a second stage of the multi-stage hierarchical analytics and caching technique. The edge cloud video headend generally implements a third stage of the multi-stage hierarchical analytics and caching technique.
Transceiver resonant receive switch
Granted: June 4, 2019
Patent Number:
10312961
An apparatus comprises an input port, an output port, and a resonant receive switch circuit. The resonant receive switch circuit may be coupled between the input port and the output port. The resonant receive switch circuit may comprise a switch and an input matching circuit. When the switch is in a non-conducting state, a signal at the input port is passed to the output port. When the switch is in a conducting state, the signal at the input port is prevented from reaching the output…
Wireless power transmitter
Granted: June 4, 2019
Patent Number:
10312736
A wireless power transmission system is presented. In some embodiments, a transmission unit includes a first inductor with a center tap, a first end tap, and a second end tap; a pre-regulator coupled to provide current to the center tap; a switching circuit coupled to the first end tap and the second end tap, the switching circuit alternately coupling the first end tap and the second end tap to ground at a frequency; and a resonant circuit magnetically coupled to the first inductor, the…
Nullifying incorrect sampled data contribution in decision feedback equalizer at restart of forwarded clock in memory system
Granted: June 4, 2019
Patent Number:
10311940
An apparatus includes a receiver circuit and a data buffer. The receiver circuit may comprise a decision feedback equalizer (DFE). The data buffer circuit may be configured to initialize a condition of the receiver circuit in response to a control signal prior to reception of a command sequence associated with a directed access to a memory system. The control signal generally indicates detection of a non-consecutive clock associated with a start of the command sequence. The data buffer…
Compensation of deterministic crosstalk in memory system
Granted: June 4, 2019
Patent Number:
10311926
An apparatus includes a detector circuit and a receiver circuit. The detector circuit may be configured to generate a control signal indicating a start of a plurality of strobe edges in a strobe signal. The receiver circuit may be configured to initialize an equalizer circuit in response to the control signal. The equalizer circuit may be configured to compensate a data signal for crosstalk coupled from the strobe edges to the data signal.
Long range beamforming and steering in wireless communication links
Granted: May 28, 2019
Patent Number:
10306484
An apparatus includes a transceiver circuit, an antenna and a focus array. The transceiver circuit may have a plurality of fed channels configured to generate a plurality of signals. The antenna may have a plurality of antenna arrays configured to generate one or more beams in response to the signals. Each antenna array may (i) have a plurality of subarrays and (ii) be coupled to the fed channels of the transceiver circuit. The focus array may have a plurality of focal zones configured…
High signal voltage tolerance in single-ended memory interface
Granted: May 28, 2019
Patent Number:
10304520
An apparatus includes a line-termination circuit and a continuous-time linear equalizer circuit. The line-termination circuit may be configured to generate a data signal in response to an input signal. The input signal generally resides in a first voltage domain. The input signal may be single-ended. The data signal may be generated in the first voltage domain. The continuous-time linear equalizer circuit may be configured to generate an intermediate signal by equalizing the data signal…
Wireless power transmitter
Granted: May 7, 2019
Patent Number:
10284015
A wireless power transmission system is presented. In some embodiments, a transmission unit includes a first inductor with a center tap, a first end tap, and a second end tap; a pre-regulator coupled to provide current to the center tap; a switching circuit coupled to the first end tap and the second end tap, the switching circuit alternately coupling the first end tap and the second end tap to ground at a frequency; and a resonant circuit magnetically coupled to the first inductor, the…
Rate-distortion optimizers and optimization techniques including joint optimization of multiple color components
Granted: April 30, 2019
Patent Number:
10277907
Examples of encoders and video encoding are described that include optimizers and techniques for optimizing syntax elements such as transform coefficients. In some examples, multiple color components of a video signal may be jointly optimized by employing a cost calculation using a combination of distortion and/or rate metrics for multiple color components. In some examples, a color transformation may occur and the optimization may take place in a different color domain than encoding. In…
Wirelessly synchronized clock networks
Granted: April 16, 2019
Patent Number:
10264542
An apparatus includes a first independently clocked device and one or more second independently clocked devices. The first independently clocked device may comprise a clock generator. The clock generator may be configured to generate a clock signal. The first independently clocked device may be configured to wirelessly broadcast a synchronization signal based on the clock signal. The one or more second independently clocked devices may each comprise respective clock generators. The one…
Entropy encoding initialization for a block dependent upon an unencoded block
Granted: April 16, 2019
Patent Number:
10264261
Apparatuses and methods for initializing a CABAC state are disclosed herein. An example apparatus may include an encoder configured to receive a macroblock dependent on at least one unencoded macroblock. The encoder may further be configured to receive a plurality of CABAC states and initialize CABAC in accordance with one of the plurality of CABAC states to encode the macroblock prior to the at least one unencoded macroblock being encoded.
Separate clock synchronous architecture
Granted: April 16, 2019
Patent Number:
10261539
An apparatus includes a plurality of independently clocked devices and a low frequency beacon. Each of the plurality of independently clocked devices has a respective local clock generator. The low frequency beacon communicates a low frequency synchronization signal to each of the independently clocked devices. The respective local clock generators of the plurality of independently clocked devices are generally synchronized using the low frequency synchronization signal.
Arbitrary delay buffer
Granted: April 2, 2019
Patent Number:
10250242
A signal may be arbitrarily delayed in discrete steps by an arbitrary delay buffer having an analog delay and a digital delay. An analog delay may have a number of selectable delay stages (e.g. ring oscillator with VCDL stages). A digital delay may have rising and falling edge detectors, resettable ring oscillators that oscillate in response to rising or falling edges and counters to count oscillations and generate rising and falling edge delay signals when oscillation counts reach…
Resynchronization of a clock associated with each data bit in a double data rate memory system
Granted: March 26, 2019
Patent Number:
10241538
An apparatus comprising an input interface, an output interface and an adjustment circuit. The input interface may comprise a plurality of input stages each configured to receive a data signal and a clock signal and present an intermediate signal. The output interface may comprise a plurality of output stages each configured to receive the intermediate signal, receive an adjusted clock signal and present an output signal. The adjustment circuit may comprise a plurality of adjustment…
Scalable coherent apparatus and method
Granted: March 19, 2019
Patent Number:
10235295
Scalable Coherent Apparatus and Method have been disclosed. In one implementation a dual directory approach is used to implement scalable coherent accesses in a heterogeneous system. A transaction identification mapping for coherent RapidIO memory transactions between a plurality of external hardware processing elements is used. Source transaction identification encoding is a combination of bits from two advanced extensible interface identifications. Target transaction identification is…
Signal driver slew rate control
Granted: March 19, 2019
Patent Number:
10236870
An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a plurality of delayed signals each as a copy of an input signal shifted in time by a sequence of respective delays based on a control signal. At least two of the respective delays may have a different duration. The first circuit may also be configured to change a number of driver signals that are active during each delay in the sequence of respective delays based on the input…
