METHOD FOR IMPROVING SENSING MARGIN OF RESISTIVE MEMORY
Granted: December 3, 2015
Application Number:
20150348624
A method in a resistive memory device includes configuring two or more memory cells in a column of the array sharing the same bit line and the same source line to operate in parallel as a merged memory cell; programming the resistance of the merged memory cell in response to the write data, the resistance of the two or more resistive memory cells in the merged memory cell being programmed simultaneously; and reading the programmed resistance value of the merged memory cell, the…
DRAM ERROR CORRECTION EVENT NOTIFICATION
Granted: November 19, 2015
Application Number:
20150331745
A method in a memory device implementing error correction includes setting an error correction event register to a first value; assessing a memory location in the first memory array in response to a memory address; retrieving stored memory data from the assessed memory location in the first memory array and retrieving error correction check bits corresponding to the assessed memory location from the second memory array; checking the retrieved memory data for bit errors using the…
FLASH MEMORY DEVICE WITH SENSE-AMPLIFIER-BYPASSED TRIM DATA READ
Granted: October 1, 2015
Application Number:
20150279473
A non-volatile memory device includes a two-dimensional array of non-volatile memory cells where a first portion of memory cells being configured as an one-time-programmable memory area; a bypass read-out circuit configured to sense a signal level on a bit line in response to a memory cell in the one-time-programmable memory area being selected and to generate a first signal indicative of the signal level on the bit line; and a trim data latch circuit having an input terminal configured…
REFERENCE CURRENT CIRCUIT WITH TEMPERATURE COEFFICIENT CORRECTION
Granted: September 24, 2015
Application Number:
20150270006
A flash memory device uses a pair of parallely connected NMOS transistors with different voltage ratings to generate the reference current for the sense amplifier used in the read out operations. The reference current thus generated is temperature compensated with zero or near-zero temperature coefficient. In some embodiments, the pair of parallely connected NMOS transistors includes a high voltage NMOS transistor and a low voltage NMOS transistor or NMOS transistors with different gate…
ABRIDGED ERASE VERIFY METHOD FOR FLASH MEMORY
Granted: August 6, 2015
Application Number:
20150221388
A non-volatile memory device includes a control circuit configured to perform a block erase operation including a block erase cycle and an erase verify cycle on a block of memory cells. The control circuit is configured to perform the erase verify cycle by storing a last verify address for each sector of the block of memory cells, verifying each memory cell in a sector starting from the last verify address for the sector until a memory cell has failed erase verification in that sector,…
ERASE ALGORITHM FOR FLASH MEMORY
Granted: July 16, 2015
Application Number:
20150200018
A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the…
ADDRESS TRANSITION DETECTING CIRCUIT
Granted: June 4, 2015
Application Number:
20150155032
There is disclosed an address transition detecting circuit in the present application. The address transition detecting circuit comprises two identical address transition detecting signal generating module, an inverter and a signal combining module. Both of the two address transition detecting signal generating module comprise a unilateral delay circuit for generating an output pulse at the rising edge of the address signal and an output pulse at the falling edge of the address signal.…
Circuit and Method for Testing Memory Devices
Granted: October 2, 2014
Application Number:
20140298120
The present application provides a circuit and method for testing a memory device. The memory device has multiple blocks addressable via a plurality of address lines and capable of inputting and/or outputting data via a plurality of data lines. The circuit comprises: a test pattern generator coupled to a first portion of the plurality of address lines to receive test data, and configured to store the test data and to generate a write test vector and a read test vector according to the…
DATA DISTRIBUTION IN CONTENT ADDRESSABLE MEMORY
Granted: November 25, 2004
Application Number:
20040236902
A data distribution system suitable for use in a content addressable memory (CAM) search engine have a number of CAM units. A set of bank multiplexers each includes a set of multiplexing constructs that are controllable via respective bank control buses. Input data for storage in the CAM units as file data or for searching against pre-stored file data are provided to the bank multiplexers and the bank control buses direct the multiplexing constructs to selectively pass sub-portions of…
Cascading Content Addressable Memory Devices with Programmable Input / Output Connections
Granted: November 18, 2004
Application Number:
20040230740
CAM devices that can be cascaded together to form CAM systems of different sizes are disclosed. The system has one or more clusters of M CAM devices, each device including (M−1) disable connections. Disable signals are used to avoid contention so that one CAM device generates the system output on a shared bus. To reduce pin count, the CAM device of priority N within each cluster has (N−1) of its disable connections programmed as inputs for disable-in signals received from…
DYNAMIC LINKING OF BANKS IN CONFIGURABLE CONTENT ADDRESSABLE MEMEORY SYSTEMS
Granted: October 28, 2004
Application Number:
20040215870
A content addressable memory (CAM) system includes CAM banks that can be linked together in a series to form a CAM module. Each CAM bank includes a CAM array with rows. In a lookup operation, each row asserts a field-match signal when a field from a key matches the field of a CAM entry held in the row. Each CAM bank receives a link-control signal, each received from the preceding CAM bank match-in signals for the rows, and each generates match-out signals for the rows. Some embodiments…
Associated Content Storage System
Granted: September 23, 2004
Application Number:
20040186972
A relocation system to associatively search a database lookup table with a search key to addressably retrieve a corresponding associate content table record as a search result. The relocation system is implemented in search engine devices having associative memory (e.g., CAM) having one or more sections. The search engine devices employ relocation values when calculating addresses, one per section per device, with the relocation values optionally pre-calculated and stored in relocation…
DUAL MATCH-LINE, TWIN-CELL, BINARY-TERNARY CAM
Granted: February 19, 2004
Application Number:
20040032758
A content addressable memory (CAM)(10, 102) and method having a data-in sub-circuit (44), memory cells (16, 18), a match-high line (36), a match-low line (38), and pre-charge devices (40, 42). Input lines (30, 32, 48, 50) from the data-in sub-circuit (44) are not necessarily discharged to ground in every cycle of a clock signal (62) used by the memory cells (16, 18). Further, the pre-charge devices (40, 42) may be operated at one half of the rate of the clock signal (62). Yet further,…
Fast aging scheme for search engine databases using a linear feedback shift register
Granted: December 25, 2003
Application Number:
20030236955
A fast aging system (10) which may work with a memory (12) in which data words (16) having aging words (18) are stored. An aging address counter (20) selects an aging word (18) for updating based on a state change in a linear feedback shift register (LFSR) (24). Optionally, in the aging word (18) a zero value (52) may represent a permanent data words (16), a predefined non-zero value (56) may represent data words (16) which are available for replacement, and other zero values may…
Search engine for large database search using CAM and hash
Granted: February 13, 2003
Application Number:
20030033276
A search engine having a controller, a memory, and at least one hash-CAM (H-CAM). The memory includes a database of search values and associate content or just associate content. The controller uses search values to access the memory to obtain the search results. The H-CAM includes at least one set of paired hash units and CAM units and at least one logic unit. The CAM units hold values known to cause hash collisions in the paired hash units, and the logic unit prioritizes the hash and…
Search engine for large database search using hash pointers
Granted: February 13, 2003
Application Number:
20030033293
A search engine (100) having a controller (112), a memory (114), and a hash pointer unit (110). The memory (114) includes a database of search data and associate content, and the controller (112) uses individual search values to access the memory (114) to obtain individual search results. The controller (112) includes a hash function (116) that generates a hash value from a, typically large, search value into a, typically smaller, hash value that may be a hash collision. The controller…
