BIOMETRIC APPROACH TO TRACK CREDENTIALS OF ANONYMOUS USER OF A MOBILE DEVICE
Granted: August 28, 2014
Application Number:
20140245408
A system includes one or more mobile devices and a shared server. Each of the one or more mobile devices is associated with a unique identification tag and configured to send biometric information about anonymous users to a shared server space. The shared server provides the shared server space. The shared server is generally configured to store biometric information about a plurality of anonymous users associated with the unique identification tag of each of the one or more mobile…
Dynamically Balanced Credit for Virtual Functions in Single Root Input/Output Virtualization
Granted: August 28, 2014
Application Number:
20140245300
A system to allow reallocation of credit among virtual machines associated with separate operating systems includes drivers in each virtual machine to independently track credit usage and a host board adapter configured to report a false maximum to each operating system and track credit usage. The host board adapter allocates credits and reports the allocated credits to virtual functions accessed by the virtual machines. A hypervisor reallocates credits by reporting the new allocation to…
MASTER BOOT RECORD PROTECTION IN A SOLID STATE DRIVE
Granted: August 28, 2014
Application Number:
20140245093
A method for protecting a master boot record in a solid state drive, comprising the steps of (A) receiving a plurality of input/output requests from a host device, (B) determining whether one or more of the input/output requests is read/written to a first of a plurality of logical block addresses of the solid state drive and (C) writing an entry to a table for each of the input/output requests read/written to the first of the logical block addresses. The table (i) is separate from the…
Test Signal Generator for Low-Density Parity-Check Decoder
Granted: August 28, 2014
Application Number:
20140245086
A method for estimating error rates in low-density parity check codes includes calibrating an encoder according to specific channel parameters and according to dominant error events in the low-density parity-check code. Dominant codewords are classified based on characteristics of each codeword that are likely to produce similar error rates at similar noise levels; codeword classes that produce the highest error rate are then tested. Error boundary distance is estimated using multiple…
MAINTAINING CACHE COHERENCY BETWEEN STORAGE CONTROLLERS
Granted: August 28, 2014
Application Number:
20140244936
Systems and methods maintain cache coherency between storage controllers utilizing bitmap data. In one embodiment, a storage controller processes an I/O request for a logical volume from a host, and generates one or more cache entries in a cache memory that is based on the request. The storage controller identifies a backup storage controller for managing the logical volume, and generates bitmap data that identifies cache entries in the cache memory that have changed since synchronizing…
METHOD AND SYSTEM TO PROVIDE DATA PROTECTION TO RAID 0/ OR DEGRADED REDUNDANT VIRTUAL DISK
Granted: August 28, 2014
Application Number:
20140244928
Disclosed is a system and method for providing redundancy to RAID 0 virtual disks by utilizing any right sized physical disk in the SAS domain. The system and method restore redundancy in a degraded redundant virtual disk. This may be done even in the absence of a configured hot spare.
FAST READ IN WRITE-BACK CACHED MEMORY
Granted: August 28, 2014
Application Number:
20140244902
An apparatus having a cache and a circuit is disclosed. The cache includes a plurality of cache lines. The cache is configured to (i) store a plurality of data items in the cache lines and (ii) generate a map that indicates a dirty state or a clean state of each of the cache lines. The cache also has a write-back policy to a memory. The circuit is configured to (i) check a location in the map corresponding to a read address of a read request and (ii) obtain read data directly from the…
Systems and Methods for Trapping Set Disruption
Granted: August 21, 2014
Application Number:
20140237313
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including utilization of different scaling values on a portion by portion basis during the data decoding.
Ratio-Adjustable Sync Mark Detection System
Granted: August 21, 2014
Application Number:
20140237329
Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for detecting a sync mark with a ratio-adjustable detection system.
Systems and Methods for Skip Layer Data Decoding
Granted: August 21, 2014
Application Number:
20140237314
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding including skipping one or more codeword blocks in the data decoding process.
Systems and Methods For Burst Demodulation
Granted: August 21, 2014
Application Number:
20140233128
A data processing circuit with flaw robust burst field demodulation includes a burst integration circuit operable to calculate burst integration results for a servo data burst field, a comparison circuit operable to determine whether an absolute value of the burst integration results falls outside a window, and an error indicating circuit operable to indicate that a media flaw has been detected when the absolute value of the burst integration results fall outside the window.
CACHE WINDOW MANAGEMENT
Granted: August 21, 2014
Application Number:
20140237193
A method of managing a plurality of least recently used (LRU) queues having entries that correspond to cached data includes ordering a first plurality of entries in a first queue according to a first recency of use of cached data. The first queue corresponds to a first priority. A second plurality of entries in a second queue are ordered according to a second recency of use of cached data. The second queue corresponds to a second priority. A first entry is selected in the first queue…
REDUCING WRITES TO SOLID STATE DRIVE CACHE MEMORIES OF STORAGE CONTROLLERS
Granted: August 21, 2014
Application Number:
20140237163
Methods and structure are provided for reducing the number of writes to a cache of a storage controller. One exemplary embodiment includes a storage controller that has a non-volatile flash cache memory, a primary memory that is distinct from the cache memory, and a memory manager. The memory manager is able to receive data for storage in the cache memory, to generate a hash key from the received data, and to compare the hash key to hash values for entries in the cache memory. The memory…
Code Forwarding and Clock Generation for Transmitter Repeaters
Granted: August 21, 2014
Application Number:
20140233668
A repeater includes a clock-and-data recovery element and a phase interpolator to extract an embedded clock frequency from a data stream. The phase interpolator determine a frequency offset and sends such offset as phase interpolator codes to a filter and scaler. The filtered, scaled phase interpolator codes are used to produce a reference clock frequency for retransmission.
PATTERN-BASED LOSS OF SIGNAL DETECTOR
Granted: August 21, 2014
Application Number:
20140233619
In described embodiments, data pattern-based detection of loss of signal (LOS) is employed for a receive path of serializer/deserializer (SerDes) devices. Pattern-based LOS detection allows for detection of data loss over variety of types of connection media, and is generally insensitive to signal attenuation. More specifically, some described embodiments disclose reliable pattern-based detection of LOS across different connection media for incoming receive data when discreet time…
HIGH SPEED NETWORK BRIDGING
Granted: August 21, 2014
Application Number:
20140233567
An apparatus having a parser and a circuit is disclosed. The parser is configured to generate a source address, a destination address and information by parsing a packet received via one of a plurality of networks. The circuit is configured to search a plurality of memories in parallel during a single cycle of operation in the apparatus. The searching includes a plurality of lookups in the memories of a plurality of data sets associated with the source address, the destination address…
ADAPTIVE ARCHITECTURE IN A CHANNEL DETECTOR FOR NAND FLASH CHANNELS
Granted: August 21, 2014
Application Number:
20140233322
An apparatus comprising a memory configured to store data and a controller. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller is configured to (i) set a value of a threshold voltage based on an estimate, (ii) determine whether the read is successful, (iii) if the read is not successful, perform a plurality of reads with a varying value of the threshold voltage, (iv) read a calibration value from a look-up…
WRITE-TRACKING CIRCUITRY FOR MEMORY DEVICES
Granted: August 21, 2014
Application Number:
20140233302
A write-tracking circuit for a writable memory array has one or more dummy memory cells and is configured to write different values to the one or more dummy memory cells. Durations of pulses applied to word lines of the memory array during write operations are controlled based on durations of writing the different values to the one or more dummy memory cells. In at least some embodiments, the write-tracking circuit is configured to write the different values to the one or more dummy…
Systems and Methods for Determining Noise Components in a Signal Set
Granted: August 21, 2014
Application Number:
20140233130
Various embodiments of the present invention provide systems and methods for estimating noise components in a received signal set. For example, one embodiment of the present invention provides a noise estimation circuit that includes a data detector circuit and a noise component calculation circuit. The data detector circuit receives a series of data samples and provides a detected output, and the noise component calculation circuit provides an electronics noise power output and a media…
NOISE PREDICTIVE FILTER ADAPTATION FOR INTER-TRACK INTERFERENCE CANCELLATION
Granted: August 21, 2014
Application Number:
20140233129
Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for adapting noise predictive filters for inter-track interference cancellation in a data processing system.
