PROGRAMMABLE CLOCK SPREADING
Granted: September 11, 2014
Application Number:
20140253203
An integrated circuit having a programmable clock spreader configured to generate a plurality of controllably skewed clock signals, each applied to a corresponding region within the integrated circuit with circuitry configured to be triggered off the applied clock signal. The programmable clock spreader is designed to enable customization of the current-demand characteristics exhibited by the integrated circuit, e.g., based on the circuit's spectral impedance profile, to cause transient…
Systems and Methods for Signal Reduction Based Data Processor Marginalization
Granted: September 4, 2014
Application Number:
20140250352
Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability, and/or operational improvement capability.
VIRTUAL FUNCTION TIMEOUT FOR SINGLE ROOT INPUT/OUTPUT VIRTUALIZATION CONTROLLERS
Granted: September 4, 2014
Application Number:
20140250338
Systems and methods presented herein provide for resetting a controller in a Single Root Input/Output Virtualization (SR-IOV) architecture. The architecture includes a physical function that periodically issues a heartbeat command to a physical function of an SR-IOV controller, starts a first timer, determines a firmware failure of the controller upon expiration of the first timer, and issues a command to reset the firmware of the controller. The architecture also includes a plurality of…
STORAGE SYSTEM DATA HARDENING
Granted: September 4, 2014
Application Number:
20140250315
A bridge receives a power down command and in response converts the power down command to a data hardening command. The bridge issues the data hardening command to a solid state disk. In response to the data hardening command, data stored on the solid state disk is hardened. The hardening comprises writing data in volatile memory to non-volatile memory. The data that is hardened comprises user data and protected data. The data hardening command optionally comprises one or more of a flush…
DECLUSTERED RAID POOL AS BACKUP FOR RAID VOLUMES
Granted: September 4, 2014
Application Number:
20140250269
Storage data is distributed across a first plurality of physical disks in a first enclosure using at least one redundant array of independent disks (RAID) technique. This creates a plurality of virtual volumes. This plurality includes at least a first virtual volume and a second virtual volume. The storage data is copied (i.e., backed up) to a second plurality of physical disks in a second enclosure. The storage data in the second enclosure is distributed across the second plurality of…
TECHNIQUES FOR REDUCING MEMORY WRITE OPERATIONS USING COALESCING MEMORY BUFFERS AND DIFFERENCE INFORMATION
Granted: September 4, 2014
Application Number:
20140250263
A system, method, and computer program product are provided for reducing write operations in memory. In use, write operations to be performed on data stored in memory are identified. A difference is then determined between results of the write operations and the data stored in the memory. Difference information associated with the difference is stored in the memory. To this end, the write operations may be reduced, utilizing the difference information.
INTELLIGENT DATA BUFFERING BETWEEN INTERFACES
Granted: September 4, 2014
Application Number:
20140250246
A dynamically controllable buffering system includes a data buffer that is communicatively coupled between first and second data interfaces and operable to perform as an elasticity first-in-first-out buffer in a first mode and to perform as a store-and-forward buffer in a second mode. The system also includes a controller that is operable to detect data rates of the first and second data interfaces, to operate the data buffer in the first mode when the first data interface has a data…
Systems and Methods for ADC Sample Based Inter-track Interference Compensation
Granted: September 4, 2014
Application Number:
20140247514
Various embodiments of the present invention provide systems and methods for mitigating inter-track interference using pre-equalized data samples.
Test Signal Generator for Low-Density Parity-Check Decoder
Granted: August 28, 2014
Application Number:
20140245086
A method for estimating error rates in low-density parity check codes includes calibrating an encoder according to specific channel parameters and according to dominant error events in the low-density parity-check code. Dominant codewords are classified based on characteristics of each codeword that are likely to produce similar error rates at similar noise levels; codeword classes that produce the highest error rate are then tested. Error boundary distance is estimated using multiple…
Dynamically Balanced Credit for Virtual Functions in Single Root Input/Output Virtualization
Granted: August 28, 2014
Application Number:
20140245300
A system to allow reallocation of credit among virtual machines associated with separate operating systems includes drivers in each virtual machine to independently track credit usage and a host board adapter configured to report a false maximum to each operating system and track credit usage. The host board adapter allocates credits and reports the allocated credits to virtual functions accessed by the virtual machines. A hypervisor reallocates credits by reporting the new allocation to…
On-Die Programming of Integrated Circuit Bond Pads
Granted: August 28, 2014
Application Number:
20140240033
SoC and SiP designs are configured with an antifuse link within the die to allow on-die programming of bond wires connecting package lead fingers to the bond pads on the die. This permits alteration of the bond pad connections for the die, particularly for the ground voltage ground signal (VSS) connections on the bond pad, at the testing stage after the die package and the power supply have been installed on the PCB. On-die programming of antifuse link allows the VSS bond pad connections…
Dedicated Memory Structure for Sector Spreading Interleaving
Granted: August 28, 2014
Application Number:
20140244926
The present disclosure is directed to a method for managing a memory. The method includes the step of receiving data, the data including a plurality of sectors. The method also includes the step of dividing each sector of the plurality of sectors into a plurality of data units. A further step of the method involves interleaving the plurality of data units to yield a plurality of interleaved data units. The method also includes the step of writing the plurality of interleaved data units…
Timing Phase Estimation for Clock and Data Recovery
Granted: August 28, 2014
Application Number:
20140241478
In order to initialize the phase of the recovered clock signal used in clock-and-data recovery (CDR) circuitry, the normal, on-line CDR processing is disabled. The sum of the absolute values of analog-to-digital converter (ADC) samples are generated for different clock phases over each unit interval (UI) of the analog signal sampled by the ADC for a specified period of time. The phase corresponding to the maximum sum is selected as the initial phase for the recovered clock signal for…
Modular, Scalable Rigid Flex Memory Module
Granted: August 28, 2014
Application Number:
20140241062
A memory card in a computer system includes a plurality of memory elements on a NAND flash board. The NAND flash board is connected to a controller board by a flexible connector. The flexible connector allows the memory elements and NAND flash controller to be physically separated so that waste heat from one does not impact the other. The flexible connector also allows elements to be organized to create an airflow channel. The airflow channel directs air in such a way as to enhance…
FAST ACCESS WITH LOW LEAKAGE AND LOW POWER TECHNIQUE FOR READ ONLY MEMORY DEVICES
Granted: August 28, 2014
Application Number:
20140241061
A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down…
REDUCED COMPLEXITY RELIABILITY COMPUTATIONS FOR FLASH MEMORIES
Granted: August 28, 2014
Application Number:
20140241056
Methods and apparatus are provided for computing reliability values, such as log likelihood ratios (LLRs), with reduced complexity for flash memory devices. Data from a flash memory device that stores M bits per cell using 2?M possible states is processed by obtaining at least two soft read voltage values corresponding to two reference voltages V0 and V1, wherein the two reference voltages V0 and V1 are between two adjacent states of the 2?M possible states; and converting the at least…
TWO-BIT READ-ONLY MEMORY CELL
Granted: August 28, 2014
Application Number:
20140241028
A read-only memory (ROM) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are connected to a second word line. The ROM cell is programmed to store any possible combination of…
ANALOG TUNNELING CURRENT SENSORS FOR USE WITH DISK DRIVE STORAGE DEVICES
Granted: August 28, 2014
Application Number:
20140240870
Amplifier architectures are provided for current sensing applications. An amplifier includes a load device, an operational amplifier, a current source, and a bipolar transistor. The operational amplifier has a first input terminal connected to a first input node that receives an input current, and a second input terminal connected to a second input node that receives a reference voltage. The current source is connected to an output of the operational amplifier. The operational amplifier,…
STORAGE DEVICE HAVING DEGAUSS CIRCUITRY CONFIGURED FOR GENERATING DEGAUSS SIGNAL WITH ASYMMETRIC DECAY ENVELOPES
Granted: August 28, 2014
Application Number:
20140240864
A hard disk drive or other storage device comprises a storage medium, a write head configured to write data to the storage medium, and control circuitry coupled to the write head. The control circuitry comprises degauss circuitry coupled to or otherwise associated with one or more write drivers. The degauss circuitry is configured to generate an asymmetric degauss signal to be applied to the write head. The asymmetric degauss signal has a waveform with upper and lower decay envelopes…
IMAGE PROCESSING METHOD AND APPARATUS FOR ELIMINATION OF DEPTH ARTIFACTS
Granted: August 28, 2014
Application Number:
20140240467
An image processing system comprises an image processor configured to identify one or more potentially defective pixels associated with at least one depth artifact in a first image, and to apply a super resolution technique utilizing a second image to reconstruct depth information of the one or more potentially defective pixels. Application of the super resolution technique produces a third image having the reconstructed depth information. The first image may comprise a depth image and…
