SYSTEM AND METHOD FOR PROVIDING CONTROLLABLE STEADY STATE CURRENT WAVESHAPING IN A HARD DISK DRIVE (HDD) PREAMPLIFIER
Granted: August 14, 2014
Application Number:
20140226234
Aspects of the disclosure pertain to a system and method for providing controllable steady state current waveshaping in a preamplifier of a data storage system (e.g., hard disk drive). The preamplifier provides an output including a write current waveform having a steady state current level that is controllable via the write block circuitry of the preamplifier. This enhances the ability of the waveform to promote improved on-track and off-track write performance.
STORAGE DEVICE WITH REFLECTION COMPENSATION CIRCUITRY
Granted: August 14, 2014
Application Number:
20140226233
A hard disk drive or other storage device comprises a storage medium, a write head configured to write data to the storage medium, and control circuitry coupled to the write head. The control circuitry comprises a write driver configured to generate a write signal comprising a write pulse, and reflection compensation circuitry coupled to or otherwise associated with the write driver and configured to provide one or more reflection compensation pulses in the write pulse.
Systems and Methods for Shared Layer Data Decoding
Granted: August 14, 2014
Application Number:
20140226229
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.
EXTENDED VARIABLE GAIN AMPLIFICATION BANDWIDTH WITH HIGH-FREQUENCY BOOST
Granted: August 14, 2014
Application Number:
20140225669
An apparatus having a circuit is disclosed. The circuit may be configured to (i) receive an input signal from a communication channel and (ii) generate an intermediate signal by amplifying the input signal (a) by a low-frequency gain in response to an amplitude control signal and (b) by a high-frequency gain in response to a boost control signal.
RADIX-4 VITERBI FORWARD ERROR CORRECTION DECODING
Granted: August 7, 2014
Application Number:
20140223267
A method for forward error correction decoding. The method generally includes steps (A) to (D). Step (A) may calculate a plurality of metrics of a codeword using a forward error correction process on a trellis having a plurality of stages. Step (B) may update the metrics over each of the stages. Step (C) may permute the metrics in each of the stages. Step (D) may generate a signal carrying a plurality of decoded bits of the codeword.
Geographic Based Spell Check
Granted: August 7, 2014
Application Number:
20140223295
The present disclosure is directed to a method for spell checking. The method includes the step of generating a geographic based list of words. The method also includes the step of appending the geographic based list of words to a spell check list. A further step of the method includes detecting a change in position. The method also includes the step of generating a new geographic based list of words when a change in position occurs.
CLASSIFYING BIT ERRORS IN TRANSMITTED RUN LENGTH LIMITED DATA
Granted: August 7, 2014
Application Number:
20140223270
A test pattern is encoded using a run length limited line encoding to produce an encoded block of data. The encoded block of data is sent via a channel. A plurality of bits in the received block of data that are subsequent to a maximum length run in the sent data is compared to an expected plurality of bits. A type of bit error is classified based on a mismatch between the expected plurality of bits and the plurality of bits in the received block of data.
Compensation Loop for Read Voltage Adaptation
Granted: August 7, 2014
Application Number:
20140219028
The disclosure is directed to a system and method for nominal read voltage variations of a flash device. N reads are performed, each at a selected voltage offset from an initial read voltage. An N bit digital pattern associated with the selected voltage offsets is generated for the N reads. The N bit digital pattern generated by the N reads is mapped to a signed representation. A voltage adjustment based upon the signed representation is applied to at least partially compensate for a…
Memory Architecture for Layered Low-Density Parity-Check Decoder
Granted: August 7, 2014
Application Number:
20140223259
A LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements.
Lookup Tables Utilizing Read Only Memory and Combinational Logic
Granted: August 7, 2014
Application Number:
20140223136
The disclosure is directed to a system and method for accessing one or more values of a lookup table. In some embodiments, one or more read only memory devices are configured for storing a first plurality of values of the lookup table, and one or more combinational logic circuits are configured for accessing a second plurality of values of the lookup table. At least one of hardware area and timing pressures are mitigated through various storage and access schemes.
Buffer for Managing Data Samples in a Read Channel
Granted: August 7, 2014
Application Number:
20140223114
The disclosure is directed to a system for managing data samples utilizing a time division multiplexing controller to allocate time slots for accessing a sample memory according to one or more modes of operation. The time division multiplexing controller is configured to allocate slots for concurrent access by a sample controller, a plurality of detectors, and a noise predictive calibrator when a normal mode is enabled. The time division multiplexing controller is further configured to…
METHOD TO THROTTLE RATE OF DATA CACHING FOR IMPROVED I/O PERFORMANCE
Granted: August 7, 2014
Application Number:
20140223106
A cache device for the caching of data and specifically for the identification of stale data or a thrashing event within the cache device is described. Further a cache device for the prioritization of cached data in the cache device during a thrashing event as well as stale cached data in the cache device are described. Methods associated with the use of the caching device for the caching of data and for the identification of data in a thrashing event or the identification of stale…
SELECTIVE RAID PROTECTION FOR CACHE MEMORY
Granted: August 7, 2014
Application Number:
20140223094
A RAID controller includes a cache memory in which write cache blocks (WCBs) are protected by a RAID-5 (striping plus parity) scheme while read cache blocks (RCBs) are not protected in such a manner. If a received cache block is an RCB, the RAID controller stores it in the cache memory without storing any corresponding parity information. When a sufficient number of WCBs to constitute a full stripe have been received but not yet stored in the cache memory, the RAID controller computes a…
PHYSICAL-TO-LOGICAL ADDRESS MAP TO SPEED UP A RECYCLE OPERATION IN A SOLID STATE DRIVE
Granted: August 7, 2014
Application Number:
20140223075
A method for increasing performance of a recycle operation in a solid state drive, comprising the steps of (A) creating an empty physical-to-logical address map in a memory having a plurality of entry locations, (B) filling one of the plurality of entry locations with a physical page address associated with each data write operation to a block, where the block has a plurality of pages, (C) writing the physical-to-logical address map to a last of the plurality of pages during a write to a…
Tiered Caching Using Single Level Cell and Multi-Level Cell Flash Technology
Granted: August 7, 2014
Application Number:
20140223072
A data storage system includes two tiers of caching memory. Cached data is organized into cache windows, and the cache windows are organized into a plurality of priority queues. Cache windows are moved between priority queues on the basis of a threshold data access frequency; only when both a cache window is flagged for promotion and a cache window is flagged for demotion will a swap occur.
METHOD AND SYSTEM FOR REDUCING WRITE LATENCY IN A DATA STORAGE SYSTEM BY USING A COMMAND-PUSH MODEL
Granted: August 7, 2014
Application Number:
20140223071
A data storage system is provided that implements a command-push model that reduces latencies. The host system has access to a nonvolatile memory (NVM) device of the memory controller to allow the host system to push commands into a command queue located in the NVM device. The host system completes each IO without the need for intervention from the memory controller, thereby obviating the need for synchronization, or handshaking, between the host system and the memory controller. For…
INTEGRATION OF SHALLOW TRENCH ISOLATION AND THROUGH-SUBSTRATE VIAS INTO INTEGRATED CIRCUIT DESIGNS
Granted: August 7, 2014
Application Number:
20140220760
A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a…
Controller-Opaque Communication with Non-Volatile Memory Devices
Granted: July 31, 2014
Application Number:
20140215123
The disclosure is directed to a system and method for controlling a non-volatile memory (NVM) device with controller-opaque commands issued by a host. A device controller is configured to receive a command script from a host. The device controller executes one or more commands of the command script including sending one or more operations of the command script to a NVM device in communication with the device controller. The device controller is enabled to provide at least a portion of…
FILE-SYSTEM AWARE SNAPSHOTS OF STORED DATA
Granted: July 31, 2014
Application Number:
20140215149
Methods and structure are provided for utilizing file-system aware backups for a Redundant Array of Independent Disks (RAID) storage system. The backup system comprises a backup storage device that includes one or more Copy-On-Write snapshots of a RAID logical volume that implements a file system. The backup system also comprises a backup controller operable to determine that a write operation is pending for an extent of the logical volume, to access allocation data for the file system…
INTEGRATED-INTERLEAVED LOW DENSITY PARITY CHECK (LDPC) CODES
Granted: July 31, 2014
Application Number:
20140215285
Methods and apparatus are provided for integrated-interleaved Low Density Parity Check (LDPC) coding and decoding. Integrated-interleaved LDPC encoding is performed by obtaining at least a first data element and a second data element; systematically encoding the at least first data element using a submatrix H0 of a sparse parity check matrix H1 to obtain at least a first codeword; truncating the at least first data element to obtain at least a first truncated data element; systematically…
