TRANSITIONING BETWEEN PAGES OF CONTENT ON A DISPLAY OF A USER DEVICE
Granted: July 31, 2014
Application Number:
20140215341
A method comprises the steps of determining an amount of time between initiating presentation of a first page in a sequence of pages on a display of a user device and receiving a transition command from a user, the transition command causing the display to transition from presentation of the first page to presentation of a second page in the sequence of pages, determining respective amounts of content in the first and second pages, estimating a rate of content consumption based at least…
INTEGRATED-INTERLEAVED LOW DENSITY PARITY CHECK (LDPC) CODES
Granted: July 31, 2014
Application Number:
20140215285
Methods and apparatus are provided for integrated-interleaved Low Density Parity Check (LDPC) coding and decoding. Integrated-interleaved LDPC encoding is performed by obtaining at least a first data element and a second data element; systematically encoding the at least first data element using a submatrix H0 of a sparse parity check matrix H1 to obtain at least a first codeword; truncating the at least first data element to obtain at least a first truncated data element; systematically…
FAST-BOOT LIST TO SPEED BOOTING AN OPERATING SYSTEM
Granted: July 31, 2014
Application Number:
20140215199
A method for booting to an operating system stored on a solid state drive. The method comprises the steps of (A) determining if a boot list has one or more entries, (B) pre-reading one or more logical block addresses of each of the entries from the boot list, (C) receiving a command from a host, (D) reading the command from a memory internal to the solid state drive if the command is in a cache area of the pre-read logical block addresses and (E) reading the command from a main portion…
Controller-Opaque Communication with Non-Volatile Memory Devices
Granted: July 31, 2014
Application Number:
20140215123
The disclosure is directed to a system and method for controlling a non-volatile memory (NVM) device with controller-opaque commands issued by a host. A device controller is configured to receive a command script from a host. The device controller executes one or more commands of the command script including sending one or more operations of the command script to a NVM device in communication with the device controller. The device controller is enabled to provide at least a portion of…
DFA SUB-SCANS
Granted: July 31, 2014
Application Number:
20140215090
In a DFA, a sub-scan is executed during a DFA scan. The sub-scan consumes input symbols out of sequence relative to the DFA scan, either forward or in reverse. An input symbol in the DFA scan is matched. A sub-scan command is supplied to the DFA. The sub-scan command is executed and at least one symbol is consumed in the sub-scan.
SYSTEM AND METHOD FOR DFA-NFA SPLITTING
Granted: July 31, 2014
Application Number:
20140214749
Cost factors are utilized and may be estimated to determine split points in a DFA-NFA hybrid. The cost factors may comprise NFA start states, DFA backup factor, DFA-NFA token frequency, DFA steps to match, and NFA states to match. Other cost factors may be used as necessary. The cost factors are multiplied by tunable coefficients and summed. NFA states at minimum cost points are determined for entrance states in the NFA. A DFA is compiled from the entrance paths to the entrance states.…
INCREMENTAL DFA COMPILATION WITH SINGLE RULE GRANULARITY
Granted: July 31, 2014
Application Number:
20140214748
A composite DFA for multiple regular expressions or other rules may be generated in a two-step process—first compiling single rule DFAs, then performing subset construction on those DFAs to generate the composite DFA, with subset information retained. A new batch of one or more rules may be added by another subset construction from the old composite DFA and new single rule DFAs, with subset information for the new composite DFA compressed into sets of states from old and new single…
AUTOMATIC GAIN CONTROL LOOP ADAPTATION FOR ENHANCED NYQUIST DATA PATTERN DETECTION
Granted: July 31, 2014
Application Number:
20140211336
Techniques are provided for automatic gain control loop adaptation in circuitry for processing such data signals. In one example, an apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry comprises an amplifier, a detector operatively coupled to the amplifier, and a feedback path operatively coupled between the detector and the amplifier. The amplifier is configured to receive and amplify an…
STORAGE ADDRESS SPACE TO NVM ADDRESS, SPAN, AND LENGTH MAPPING/CONVERTING
Granted: July 24, 2014
Application Number:
20140208062
Storage address space to NVM address, span, and length mapping/converting is performed by a controller for a solid-state storage system that includes a mapping function to convert a logical block address from a host to an address of a smallest read unit of the NVM. The mapping function provides span and length information corresponding to the logical block address. The span information specifies a number of contiguous smallest read units to read to provide data (corresponding to the…
AT-SPEED SCAN TESTING OF CLOCK DIVIDER LOGIC IN A CLOCK MODULE OF AN INTEGRATED CIRCUIT
Granted: July 24, 2014
Application Number:
20140208175
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a scan chain having a plurality of scan cells. The integrated circuit further comprises a clock distribution network configured to provide clock signals to respective portions of the integrated circuit. The clock distribution network comprises at least one clock module comprising one or more clock dividers and associated…
CAPACITIVE COUPLED SENSE AMPLIFIER BIASED AT MAXIMUM GAIN POINT
Granted: July 24, 2014
Application Number:
20140204659
A sense amplifier includes a first inverter including a first input node and a first output node, the first input node coupled to a first bitline through a first capacitor, the first output node coupled to a second bitline through a second capacitor, a second inverter including a second input node and a second output node, the second input node coupled to the second bitline through the second capacitor, the second output node to the first bitline through the first capacitor, a first…
System and Methods for Performing Embedded Full-Stripe Write Operations to a Data Volume With Data Elements Distributed Across Multiple Modules
Granted: July 24, 2014
Application Number:
20140208024
A data storage system and methods for managing data to be transferred between a host and a data volume distributed across solid state storage modules are disclosed. A storage controller couples the host to the data volume and manages data transfers to and from the logical volume. The storage controller receives a set of parameters that define how an array of blocks and chunks of buffered data will be distributed across solid state storage modules. The storage controller receives and…
VARIABLE-SIZE FLASH TRANSLATION LAYER
Granted: July 24, 2014
Application Number:
20140208003
A method for using a variable-size flash transition layer is disclosed. Step (A) receives a read request to read data corresponding to a logical block address from a nonvolatile memory. Step (B) reads a particular entry of a map to obtain (i) a physical address of a particular page of the nonvolatile memory, (ii) an offset in the particular page to compressed data previously stored and (iii) a length of the compressed data. The particular entry is associated with the logical block…
HYBRID HARD DISK DRIVE HAVING A FLASH STORAGE PROCESSOR
Granted: July 24, 2014
Application Number:
20140207996
An apparatus is described that is configured to control operations in a hybrid hard disk drive. In an implementation, the apparatus includes a hybrid flash storage processor connected to the host interface that is configured to communicatively couple a flash storage component and to a hard disk integrated circuit chip. The integrated circuit chip includes a read/write channel device configured to communicatively couple to a hard disk drive assembly and a hard disk drive controller…
Method for Storage Driven De-Duplication of Server Memory
Granted: July 24, 2014
Application Number:
20140207743
A method for storage driven de-duplication of server memory comprises configuring a storage controller, as part of each IO operation, to generate a unique signature for each data page passing through the controller. The method associates the signature with the data page and stores the associated page and signature. The signature is added to a signature queue for signature match analysis with signatures stored in server memory. Signature analysis is limited to read-only pages to speed up…
METHOD AND APPARATUS FOR MPEG-2 TO H.264 VIDEO TRANSCODING
Granted: July 24, 2014
Application Number:
20140205005
A method for transcoding from an MPEG-2 format to an H.264 format is disclosed. The method generally comprises the steps of (A) decoding an input video stream in the MPEG-2 format to generate a plurality of macroblocks; (B) determining a plurality of indicators from a pair of the macroblocks, the pair of the macroblocks being vertically adjoining; and (C) coding the pair of the macroblocks into an output video stream in the H.264 format using one of (i) a field mode coding and (ii) a…
EFFICIENT REGION OF INTEREST DETECTION
Granted: July 24, 2014
Application Number:
20140204995
An apparatus having a circuit is disclosed. The circuit may be configured to (i) calculate a plurality of complexity values while compressing a current picture in a video signal. Each complexity value generally characterizes how a corresponding one of a plurality of blocks in the current picture was compressed. The circuit may also be configured to (ii) adjust the complexity values below a first threshold to a default value and (iii) generate a region of interest by grouping the blocks…
System and Method for Determining Channel Loss in a Dispersive Communication Channel at the Nyquist Frequency
Granted: July 24, 2014
Application Number:
20140204987
The present invention includes receiving a signal from an output of a dispersive communication channel established between a transmitter and a receiver, determining normalized Nyquist energy of the signal transmitted along the dispersive communication channel established between the transmitter and the receiver, and generating a mapping table configured to identify peaking value at or above a selected tolerance level at or near the Nyquist frequency for a signal received by the receiver…
MARGIN FREE PVT TOLERANT FAST SELF-TIMED SENSE AMPLIFIER RESET CIRCUIT
Granted: July 24, 2014
Application Number:
20140204683
In described embodiments, a circuit for providing a margin free PVT tolerant fast self-timed sense amplifier reset includes a sense amplifier coupled between a complementary pair of first and second bitlines in a memory cell, a first and second PMOS drivers connected to internal nodes of the sense amplifier, respectively, and outputting a first and second output signals, wherein the second output signal is inverted by an inverter to form an inverted output signal, a read detect block…
MEMORY HAVING SENSE AMPLIFIER FOR OUTPUT TRACKING BY CONTROLLED FEEDBACK LATCH
Granted: July 24, 2014
Application Number:
20140204660
In described embodiments, a memory circuit includes a static random access memory (SRAM) including N banks of memory cells, rows of M sense amplifiers, a controlled feedback latch storing a previous state of input data in a read cycle, a pull down select block coupled to the controlled feedback latch and the dummy sense amplifier, a dummy output latch coupled to the pull-down select block to store the read data, and a SRAM reset generation circuit coupled to the sense amplifier control…
