Reading Data from Hard Disks Having Reduced Preambles
Granted: August 27, 2015
Application Number:
20150243321
An exemplary hard disk (HD) track has a full overhead section followed by user sections interleaved with intervening partial overhead sections that are too short for an HD drive (HDD) to attain sufficient timing lock using only one partial overhead section, but long enough for the drive to attain sufficient timing lock using multiple partial overhead sections to read user data from the user section immediately following the partial overhead section where sufficient timing lock is…
Systems and Methods for Synchronization Hand Shaking in a Storage Device
Granted: August 27, 2015
Application Number:
20150243311
Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for reporting a synchronization indication and for applying a synchronization window. As an example, a system is discussed that includes: a head assembly including a first read head and a second read head; a down track distance calculation circuit operable to calculate a down track distance between the first read head and the second read head; and a synchronization mark detection…
Systems and Methods for Multi-Head Separation Determination
Granted: August 27, 2015
Application Number:
20150243310
Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly.
STORAGE WORKLOAD HINTING
Granted: August 27, 2015
Application Number:
20150242133
Methods and structure for reconfiguring storage systems are provided. One exemplary embodiment is a storage controller. The storage controller includes a memory that stores multiple profiles that are each designated for a different type of Input/Output processing workload from a host, and each include settings for managing communications with coupled storage devices. Each type of workload is characterized by a pattern of Input/Output requests from the host. The storage controller also…
Method and Apparatus for Pre-Cursor Intersymbol Interference Correction
Granted: August 20, 2015
Application Number:
20150236875
A multi-stage system and method for correcting intersymbol interference is disclosed. The system includes a first estimation module configured to sample an input signal to produce a first set of estimated data bits. The system also includes a second estimation module configured to sample the input signal phase shifted by a predetermined phase shift unit to produce a second set of estimated data bits, wherein the second set of estimated data bits are produced at least partially based on…
Refresh, Run, Aggregate Decoder Recovery
Granted: August 20, 2015
Application Number:
20150236726
A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.
SYSTEM TO CONTROL A WIDTH OF A PROGRAMMING THRESHOLD VOLTAGE DISTRIBUTION WIDTH WHEN WRITING HOT-READ DATA
Granted: August 20, 2015
Application Number:
20150235705
An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to write user data using a plurality of threshold voltages. The data considered hot-read data is written using a first voltage threshold. The data not considered hot-read data is written using a second voltage…
Baud Rate Phase Detector with No Error Latches
Granted: August 20, 2015
Application Number:
20150234423
Phase detectors and timing recovery techniques that do not require error latches nor oversampling of the received input data are disclosed. The phase detection method includes separating an input signal into N consecutive data bits; comparing at least two consecutive data bits within the N consecutive data bits; estimating a data bit value for each of the N consecutive data bits; and determining a phase difference based on a data bit pattern formed by the data bit values of the N…
Systems and Methods for End of Fragment Marker Based Data Alignment
Granted: August 13, 2015
Application Number:
20150228304
Systems and method relating generally to data processing, and more particularly to systems and methods for data synchronization and detection.
MITIGATION OF WRITE ERRORS IN MULTI-LEVEL CELL FLASH MEMORY THROUGH ADAPTIVE ERROR CORRECTION CODE DECODING
Granted: August 13, 2015
Application Number:
20150229337
An apparatus includes a controller and an adaptive error correction code decoder. The controller may be configured to read data from and write data to a memory device. The controller may be further configured to write data in a two-step process, which includes (i) after writing data to a least significant bit (LSB) page, checking the data stored in the LSB page using a first strength error correction code (ECC) decoding process and (ii) after writing data to a most significant bit (MSB)…
Read Channel Sampling Utilizing Two Quantization Modules for Increased Sample Bit Width
Granted: August 13, 2015
Application Number:
20150228303
A communication channel structure and a decoding method supported by such a communication channel structure are disclosed. Such a communication channel includes a digital filter configured for filtering an input signal and two quantizer configured for quantizing the filtered signal. A first quantizer is utilized to quantize the filtered signal to produce a first quantized sample having a first precision and a second quantizer is utilized to quantize the filtered signal to produce a…
Zero Phase Start Estimation in Readback Signals
Granted: August 13, 2015
Application Number:
20150228302
A data storage system identifies analog-to-digital conversion samples with amplitude below a certain threshold. Remaining samples are grouped according to phase into one or more quadrants. A multi-coordinate with overlapping quadrants is used to further differentiate sample points. The system then computes an average phase for zero phase start estimation.
HOT-READ DATA AGGREGATION AND CODE SELECTION
Granted: August 13, 2015
Application Number:
20150227418
An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to (i) classify data from multiple blocks of the memory as hot-read data or non hot-read data, (ii) aggregate the hot-read data to dedicated blocks, and (iii) select a type of error correcting code to protect the…
Decoding System and Method for Electronic Non-Volatile Computer Storage Apparatus
Granted: August 13, 2015
Application Number:
20150227403
Methods are systems for calculating log-likelihood ratios for a decoder utilized in an electronic non-volatile computer storage apparatus are disclosed. A log-likelihood ratio handler is configured to provide an input log-likelihood ratio to the decoder, wherein the input log-likelihood ratio is one of: a uniform input log-likelihood ratio for all bits calculated based on an estimated raw bit error rate for a particular data unit, or a bit-based input log-likelihood ratio for each bit…
Systems and Methods for Last Written Page Handling in a Memory Device
Granted: August 13, 2015
Application Number:
20150227314
Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory.
READER SEPARATION DEPENDENT LINEAR AND TRACK DENSITY PUSH FOR ARRAY READER BASED MAGNETIC RECORDING
Granted: August 6, 2015
Application Number:
20150221333
A method of operating a multi-reader two-dimensional magnetic recording system includes determining a position of a multi-reader head of the multi-reader two-dimensional magnetic recording system, determining an areal density push according to the position of the multi-reader head, and performing an operation to read data from or write data to a magnetic recording medium according to the areal density push.
SYSTEM FOR EXECUTION OF SECURITY RELATED FUNCTIONS
Granted: August 6, 2015
Application Number:
20150220744
An apparatus having a first memory circuit, a plurality of arithmetic modules, and a plurality of second memory circuits. The first memory circuit may be configured to read or write data to or from a host. The plurality of arithmetic modules each may be configured to be enabled or disabled in response to control signals received from the first memory circuit. The plurality of second memory circuits may be configured to read or write data to or from the first memory circuit through a data…
System, Method and Computer-Readable Medium for Dynamically Mapping a Non-Volatile Memory Store
Granted: August 6, 2015
Application Number:
20150220452
Applications that use non-volatile random access memory (NVRAM), such as those that apply file system journal writes and database log writes where write operations apply data sequentially over the NVRAM, map the available capacity of the NVRAM in a virtual address space without compromising performance. The NVRAM is segmented into regions with multiple such regions fitting within a volatile RAM element accessible to the application and the NVRAM. One or more regions are loaded in the…
Systems and Methods for Hard Error Reduction in a Solid State Memory Device
Granted: August 6, 2015
Application Number:
20150220388
Systems and method relating generally to solid state memory, and more particularly to systems and methods for reducing errors in a solid state memory.
INTEGRATED READ/WRITE TRACKING IN SRAM
Granted: July 30, 2015
Application Number:
20150213881
Systems and methods presented herein provide for integrated read/write tracking in an SRAM device. In one embodiment, an SRAM device includes a clock, a memory cell array, a column of dummy bit cells operable to mirror bit line loading of the memory cell array, and a row of dummy bit cells operable to mirror word line loading of the memory cell array. The SRAM devices also includes a read/write tracking cell operable to track read operations from the memory cell array via the dummy bit…
