MULTI-CORE ARCHITECTURE FOR LOW LATENCY VIDEO DECODER
Granted: July 23, 2015
Application Number:
20150208076
An apparatus having first, second and third processors of a multi-core processor is disclosed. The first processor is configured to perform one or more first operations in a decoding of a plurality of macroblocks of video in a bitstream. The second processor (i) operates as a slave to the first processor and (ii) is configured to perform one or more second operations in the decoding of the macroblocks. The third processor (i) operates as a slave to the second processor and (ii) is…
Modular Low Power Serializer-Deserializer
Granted: July 23, 2015
Application Number:
20150207648
Modular, low power serializer-deserializer receivers and methods for configuring such receivers are disclosed. The disclosed receivers are configured to sample input signals at the front-end utilizing a plurality of track-and-hold circuits time-interleaved based on a plurality of phase-shifted clock signals. The disclosed receivers are also modular and various processing components, including analog front-end and equalizers, are selectively utilized based on the determined length of the…
HIGH DENSITY MAPPING FOR MULTIPLE CONVERTER SAMPLES IN MULTIPLE LANE INTERFACE
Granted: July 23, 2015
Application Number:
20150205752
An apparatus having a plurality of buffers, a first circuit and a second circuit is disclosed. The buffers are configured to store a plurality of frames to be transmitted in a plurality of respective lanes of a communication channel. The first circuit is configured to (i) generate a plurality of first groups from a first number of a plurality of samples, at least one of the first groups contains an initial portion of a given one of the samples, and (ii) generate a first of the frames by…
INTERLEAVING CODEWORDS OVER MULTIPLE FLASH PLANES
Granted: July 16, 2015
Application Number:
20150199140
An apparatus having an interface to a plurality of memories and a circuit is disclosed. Each memory generally has a plurality of planes and is nonvolatile. The circuit is configured to (i) generate a plurality of codewords by encoding a plurality of data units, (ii) generate a plurality of slices by parsing the codewords, (iii) generate a plurality of pages by interleaving the slices and (iv) write the pages in parallel into respective ones of the planes.
Segmented Digital-To-Analog Converter With Overlapping Segments
Granted: July 16, 2015
Application Number:
20150200681
In one embodiment, a segmented digital-to-analog converter (DAC) has two configurations (i.e., sub-DACs) with overlapping operating ranges and a data mapper that maps the digital input signal into two different digital signals, one for each sub-DAC. The currents generated by the sub-DACs are combined and then used to generate the corresponding analog output signal. Because the sub-DACs have overlapping operating ranges, the DAC can be calibrated to account for process variations that…
Multiple Track Detection
Granted: July 16, 2015
Application Number:
20150199991
An apparatus for reading data includes an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium, wherein the analog inputs correspond to multiple data tracks on the magnetic storage medium, and wherein the number of analog inputs in the array of analog inputs is greater than the number of data tracks being read, at least one joint equalizer operable to filter the analog inputs to yield an equalized output for each of the data tracks being…
ENHANCED SSD CACHING
Granted: July 16, 2015
Application Number:
20150199269
An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the plurality of cache-lines may be associated with meta-data indicating one or more of a dirty state and an invalid state. The controller may be connected to the memory and configured to detect an…
INTELLIGENT I/O CACHE REBUILD IN A STORAGE CONTROLLER
Granted: July 16, 2015
Application Number:
20150199244
Systems and methods presented herein provide for redundancy in I/O caching. In one embodiment, a storage controller includes a first cache operable to receive input/output requests between a host system and a storage device, to compress data of the input/output requests, and to cache the compressed data before writing to the storage device. The storage controller also includes a second cache operable to track chunks of the compressed data in the first cache. When the first cache fails,…
Fault Detection and Identification in a Multi-Initiator System
Granted: July 16, 2015
Application Number:
20150199227
A storage system and method for identifying a faulty link the storage system is disclosed. The storage system includes a plurality of target devices and at least one expander configured to communicatively couple a plurality of initiators to the plurality of target devices. Each initiator of the plurality of initiators monitors occurrences of link disruptions independently, wherein upon detecting occurrences of a predetermined number of link disruptions within a predetermined time period,…
FRAMEWORK FOR BALANCING ROBUSTNESS AND LATENCY DURING COLLECTION OF STATISTICS FROM SOFT READS
Granted: July 16, 2015
Application Number:
20150199149
An apparatus includes a plurality of memory devices and a controller. The controller is coupled to the plurality of memory devices and configured to store data in the plurality of memory devices using units of super-blocks. Each super-block comprises a block from each of the plurality of memory devices and the controller balances time efficiency and robustness during collection of statistics from soft reads of each super-block.
System and Method for Providing Data Services in Direct Attached Storage via Multiple De-clustered RAID Pools
Granted: July 16, 2015
Application Number:
20150199129
A system and method for providing Quality of Service (QoS)-based data services in a direct attached storage system including at least one physical drive comprises logically dividing the drive or drives into a plurality of pools implemented according to CRUSH algorithms or other declustered RAID configurations. The plurality of pools are then managed as declustered RAID virtual drives. The system and method further comprises identifying a pool with a performance characteristic and…
ENHANCING ACTIVE LINK UTILIZATION IN SERIAL ATTACHED SCSI TOPOLOGIES
Granted: July 9, 2015
Application Number:
20150195357
Methods and systems are provided for enhanced link utilization in attached SCSI (SAS) topologies. A SAS expander may be configured to monitor link utilization within a SAS topology, and may manage connection requests received thereby based on the monitoring of link utilization. The monitoring may comprise determining availability of links for at least one node within the SAS topology with respect to other nodes in the SAS topology. This may be done based on pending connection requests,…
RECEIVER WITH PIPELINED TAP COEFFICIENTS AND SHIFT CONTROL
Granted: July 9, 2015
Application Number:
20150195108
A serializer-deserializer using series-coupled signal processing blocks to process digitized input symbols, each block having a coefficient input. Each of plurality of series-coupled coefficient delay elements has a control input and a coefficient output coupling to the coefficient inputs of a corresponding one of the signal processing modules, is controlled by a shift register having an input and a plurality of outputs, each one of the plurality of outputs coupled to the control input…
CAPACITANCE COUPLING PARAMETER ESTIMATION IN FLASH MEMORIES
Granted: July 9, 2015
Application Number:
20150194219
A method for capacitance coupling parameter estimation is disclosed. Step (A) of the method determines a plurality of voltages in a plurality of memory cells of a nonvolatile memory in response to a plurality of writes to the memory cells. The voltages are determined in each of a plurality of cases related to inter-cell interference. Step (B) generates a system of equations of a capacitance coupling model in response to the voltages from all of the cases. Step (C) generates one or more…
SYSTEM AND METHOD FOR USING CLOCK CHAIN SIGNALS OF AN ON-CHIP CLOCK CONTROLLER TO CONTROL CROSS-DOMAIN PATHS
Granted: July 9, 2015
Application Number:
20150193564
An on-chip clock controller configured to control cross-domain paths using clock chain signals is disclosed. The on-chip clock controller includes a clock bits module configured to receive a clock chain signal and to output an enable signal based upon the clock chain signal. The on-chip clock controller also includes a clock gating module that is communicatively coupled to the clock bits module. The clock gating module is configured to receive a clock signal and to selectively output…
Systems and Methods for Efficient Targeted Symbol Flipping
Granted: July 2, 2015
Application Number:
20150188576
Systems and method relating generally to data processing, and more particularly to systems and methods for modifying symbols in a data set prior to re-processing.
CLOCK RECOVERY USING QUANTIZED PHASE ERROR SAMPLES USING JITTER FREQUENCY-DEPENDENT QUANTIZATION THRESHOLDS AND LOOP GAINS
Granted: July 2, 2015
Application Number:
20150188551
A clock and data recovery device includes a phase detector, a quantizer, and a loop filter. The phase detector produces a phase error samples at an output representing a phase difference between a phase-adjusted clock and an input data signal. The quantizer, coupled to the output of the phase detector and responsive to high threshold and low threshold values, produces a tri-valued quantized phase error samples at an output. The loop filter filters either the quantized phase error samples…
Systems and Methods for Multi-Head Balancing in a Storage Device
Granted: July 2, 2015
Application Number:
20150187385
Systems and method relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device.
TWO-DIMENSIONAL MAGNETIC RECORDING READER OFFSET ESTIMATION
Granted: July 2, 2015
Application Number:
20150187384
A method for enhancing read performance in a multi-reader two-dimensional magnetic recording system comprising first and second readers includes: receiving first and second analog read signals from the first and second readers, respectively; sampling the first and second analog read signals to generate first and second sampled signals, respectively, each of the first and second sampled signals comprising an integer component, indicative of a value of a corresponding one of the first and…
SYSTEM FOR EFFICIENT CACHING OF SWAP I/O AND/OR SIMILAR I/O PATTERN(S)
Granted: June 25, 2015
Application Number:
20150178201
An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache may comprise one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. The controller is connected to the memory and configured to (A) process normal read/write operations in a first mode and (B) process special read/write operations in a second mode by (i) tracking a write…
