HASH PROCESSING IN A NETWORK COMMUNICATIONS PROCESSOR ARCHITECTURE
Granted: September 15, 2011
Application Number:
20110225391
Described embodiments provide a hash processor for a system having multiple processing modules and a shared memory. The hash processor includes a descriptor table with N entries, each entry corresponding to a hash table of the hash processor. A direct mapped table in the shared memory includes at least one memory block including N hash buckets. The direct mapped table includes a predetermined number of hash buckets for each hash table. Each hash bucket includes one or more hash key and…
SYSTEM AND METHOD FOR OPTIMIZING REDUNDANCY RESTORATION IN DISTRIBUTED DATA LAYOUT ENVIRONMENTS
Granted: September 15, 2011
Application Number:
20110225453
The present disclosure is directed to a system and a method for optimizing redundancy restoration in distributed data layout environments. The system may include a plurality of storage devices configured for providing data storage. The system may include a prioritization module communicatively coupled to the plurality of storage devices. The prioritization module may be configured for determining a restoration order of at least a first data portion and a second data portion when a…
EXCEPTION DETECTION AND THREAD RESCHEDULING IN A MULTI-CORE, MULTI-THREAD NETWORK PROCESSOR
Granted: September 15, 2011
Application Number:
20110225589
Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A function bus interface inspects instructions received from the multi-thread…
DATA PREFETCH FOR SCSI REFERRALS
Granted: September 15, 2011
Application Number:
20110225371
A method for communication between an initiator system and a storage cluster. The method comprises receiving an initial I/O request from the initiator system to a first storage system; providing a referral response from the first storage system to the initiator system, the referral response providing information for directing the initiator system to a second storage system; notifying the second storage system regarding the referral response via a prefetch notice, the prefetch notice…
I/O and Power ESD Protection Circuits By Enhancing Substrate-Bias in Deep-Submicron CMOS Process
Granted: September 8, 2011
Application Number:
20110215410
A technique for enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well…
SYSTEM AND METHOD FOR PROVIDING ADDRESS DECODE AND VIRTUAL FUNCTION (VF) MIGRATION SUPPORT IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) MULTI-ROOT INPUT/OUTPUT VIRTUALIZATION (IOV) ENVIRONMENT
Granted: September 8, 2011
Application Number:
20110219161
The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment. The method may include receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment. The method may further include comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each…
Interconnects using Self-timed Time-Division Multiplexed Bus
Granted: September 1, 2011
Application Number:
20110211582
A method of sending signals, including data and timing information, between transportation units on a communication bus of an integrated circuit, by generating clock triggers for every transportation unit on the bus, thereby initiating each preceding one of the transportation units to start sending the signals in a wave-front to an adjacent succeeding one of the transportation units, where the wave-front is initiated at each of the transportation units at a common point in time, and…
METHODS AND APPARATUS FOR MANAGING CACHE PERSISTENCE IN A STORAGE SYSTEM USING MULTIPLE VIRTUAL MACHINES
Granted: August 18, 2011
Application Number:
20110202728
Methods and systems for assuring persistence of battery backed cache memory in a storage system comprising multiple virtual machines. In one exemplary embodiment, an additional process is added to the storage controller that senses the loss of power and copies the entire content of the cache memory including portions used by each of the multiple virtual machines to a nonvolatile persistent storage that does not rely on the battery capacity of the storage system. In another exemplary…
REDUNDANT ARRAY OF INDEPENDENT STORAGE
Granted: August 18, 2011
Application Number:
20110202721
A data storage system includes three or more storage devices, each associated with a unique data volume. A first one of the data storage devices at least has two or more data storage areas but can have more storage areas, which can be either data storage areas or parity storage areas. A second data storage device at least has two storage areas, one of which is a data storage area. A third data storage device at least has a parity storage area but can have more storage areas, which can be…
HIGH-PERFORMANCE TONE DETECTION USING A DIGITAL SIGNAL PROCESSOR (DSP) HAVING MULTIPLE ARITHMETIC LOGIC UNITS (ALUS)
Granted: August 18, 2011
Application Number:
20110200147
In one embodiment, a DSP having four arithmetic logic units (ALUs) and able to have two read/write operations per clock cycle performs silence detection and tone detection for data frames containing samples of an audio signal. The ALUs are used together in parallel to process the samples in the data frames received by the DSP. A received data frame is filtered by the silence detection so that substantially silent frames are dropped and non-silent frames are further processed. In the tone…
FREQUENCY-BASED APPROACH FOR DETECTION AND CLASSIFICATION OF HARD-DISC DEFECT REGIONS
Granted: August 18, 2011
Application Number:
20110199699
In a hard-disc drive read channel, frequency-based measures are generated at two different data frequencies (e.g., 2T and DC) by applying a transform, such as a discrete Fourier transform (DFT), to signal values, such as ADC or equalizer output values, corresponding to, e.g., a 2T data pattern stored on the hard disc. The frequency-based measures are used to detect defect regions on the hard disc and/or to classify defect regions as being due to either thermal asperity (TA) or drop-out…
SYSTEM AND METHOD FOR QoS-BASED STORAGE TIERING AND MIGRATION TECHNIQUE
Granted: August 11, 2011
Application Number:
20110197027
The present invention is directed to a method for providing Quality Of Service (QoS)-based storage tiering and migration in a storage system. The method allows for configurable application data latency thresholds to be set on a per user basis and/or a per application basis so that a storage tiering mechanism and/or a storage migrating mechanism may be triggered for moving application data to a different class of storage.
Modular and Redundant Data-Storage Controller And a Method for Providing a Hot-Swappable and Field-Serviceable Data-Storage Controller
Granted: July 28, 2011
Application Number:
20110185099
A modular and redundant storage controller system includes management modules, controller modules and an interconnect module. The management modules provide direct-current power and signals to respective controller modules. The controller modules include respective signal interfaces, direct-current interfaces, and interconnect interfaces. The signal interfaces couple the controllers to a respective management module. The direct-current interfaces couple the controllers to a respective…
METHOD FOR PLACEMENT OF VIRTUAL VOLUME HOT-SPOTS IN STORAGE POOLS USING ONGOING LOAD MEASUREMENTS AND RANKING
Granted: July 28, 2011
Application Number:
20110185120
The present invention is directed to a method for providing data element placement in a storage system via a Dynamic Storage Tiering (DST) mechanism, such that improved system efficiency is promoted. For example, the DST mechanism may implement an algorithm for providing data element placement. The data elements (ex.—virtual volume hot-spots) may be placed into storage pools, such that usage of higher performing storage pools is maximized. Hot-spots may be detected by dynamically…
EXECUTING WATCHPOINT EVENTS FOR DEBUGGING IN A "BREAK BEFORE MAKE" MANNER
Granted: July 28, 2011
Application Number:
20110185156
A processor (e.g., a Digital Signal Processor (DSP) core) rewinds a pipeline of instructions upon a watchpoint event in an instruction being processed. The program execution ceases at the instruction in which the watchpoint event occurred, while the instruction and subsequent instructions are cancelled, keeping the hardware components associated with executing the program in their previous states, prior to the watchpoint. The rewind is such that the program is refetched to enable…
INTEGRATED HEAT SINK
Granted: July 21, 2011
Application Number:
20110176278
An electronic device includes a heat dissipating component located over a substrate. An isolation trench is formed in the substrate adjacent the component. A contact region of the substrate is bounded by the trench. An electrically isolated contact is located over and in contact with the contact region. The electrically isolated contact and the contact region provide a thermally conductive path to the substrate.
ACTIVE-ACTIVE FAILOVER FOR A DIRECT-ATTACHED STORAGE SYSTEM
Granted: July 14, 2011
Application Number:
20110169254
Airbag inflators employ gas generating compositions formed from a mixture of fuels and a mixture of oxidizers and preferably mica at levels of 1 to 5% by weight. The gas generant composition contains a primary and secondary fuel. The primary fuel is a guanidine compound, preferably guanidine nitrate. The secondary fuel is selected from tetrazoles, triazoles and mixtures thereof at levels of 5% by weight or less of the total gas generant composition. The oxidizer system is a mixture of at…
Parallel LDPC Decoder
Granted: July 14, 2011
Application Number:
20110173510
An LDPC decoder that implements an iterative message-passing algorithm, where the improvement includes a pipeline architecture such that the decoder accumulates results for row operations during column operations, such that additional time and memory are not required to store results from the row operations beyond that required for the column operations.
THREE-STAGE ARCHITECTURE FOR ADAPTIVE CLOCK RECOVERY
Granted: July 7, 2011
Application Number:
20110164627
An adaptive clock recovery (ACR) system has a first closed-loop control processor (e.g., a first proportional-integral (PI) processor) that processes an input phase signal indicative of jittery packet arrival times to generate a mean phase reference. The input phase signal is compared to the mean phase reference to generate delay-offset values that are indicative of the delay-floor corresponding to the packet arrival times. The mean phase reference and the delay-offset values are used to…
ADAPTIVE CLOCK RECOVERY WITH STEP-DELAY PRE-COMPENSATION
Granted: July 7, 2011
Application Number:
20110164630
An adaptive clock recovery (ACR) subsystem processes an input phase signal indicative of jittery packet arrival times to generate a relatively smooth and bounded output phase signal that can be used to generate a relatively stable recovered clock signal. The input phase signal is also processed to detect and measure step-delays corresponding, for example, to path changes in the network routing of the packets. Step-delay pre-compensation is performed, in which the input phase signal is…
