SYSTEMS AND METHODS FOR INSTALLING A BOOTABLE VIRTUAL STORAGE APPLIANCE ON A VIRTUALIZED SERVER PLATFORM
Granted: March 31, 2011
Application Number:
20110078433
One embodiment is a method for installing a virtual storage appliance on a host server platform. One such method comprises: providing an installation package to a host server platform, the installation package comprising an installation script for installing an I/O virtual machine (IOVM), an IOVM boot console, and an IOVM management module; running the installation script to create a hidden boot partition on a boot disk and copy the IOVM boot console and the IOVM management module to the…
METHOD AND SYSTEM FOR DYNAMIC STORAGE TIERING USING ALLOCATE-ON-WRITE SNAPSHOTS
Granted: March 31, 2011
Application Number:
20110078398
The present disclosure describes a systems and methods for dynamic storage tiering A method for dynamic storage tiering may comprise: creating a point-in-time copy of a virtual volume including a storage hot-spot; copying a virtual volume segment including the hot-spot from a first storage pool to a second storage pool; and reconfiguring a logical block address mapping of the virtual volume to reference the virtual volume segment copy in the second storage pool. A system for dynamic…
SNAPSHOT METADATA MANAGEMENT IN A STORAGE SYSTEM
Granted: March 24, 2011
Application Number:
20110072224
Methods and systems for improving performance in a storage system utilizing snapshots are disclosed by using metadata management of snapshot data. Specifically, various metadata structures associated with snapshots are utilized to reduce the number of IO operations required to locate data within any specific snapshot. The number of IO operations are reduced by allowing the various metadata structures associated with the temporally current snapshot to locate data directly within any…
BRANCH-METRIC CALIBRATION USING VARYING BANDWIDTH VALUES
Granted: March 24, 2011
Application Number:
20110072335
In one embodiment, a signal processing receiver has a branch-metric calibration (BMC) unit that receives (i) sets of four hard-decision bits from a channel detector and (ii) a noise estimate. The BMC unit has two or more update blocks (e.g., tap-weight update and/or bias-compensation blocks) that generate updated parameters used by a branch-metric unit of the channel detector to improve channel detection. The two or more update blocks generate the updated parameters based on (i) the sets…
Write Through Speed Up for Memory Circuit
Granted: March 17, 2011
Application Number:
20110063926
A method of performing a write-through operation with a memory circuit having a write enable line, a write address line, a data in line, a read address line, a data out line, a bit array, a comparator, and a mux. A write address is received on the write address line, a read address is received on the read address line, data is received on the data in line. The comparator determines as a first condition whether the write address is identical to the read address, and determines as a second…
Test Pin Gating for Dynamic Optimization
Granted: March 17, 2011
Application Number:
20110066905
An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional…
SIGNAL PROCESSING USING MODIFIED BLOCKWISE ANALYTIC MATRIX INVERSION
Granted: March 10, 2011
Application Number:
20110058619
In one embodiment, a method for signal processing is provided that uses an improved inversion to mitigate the imprecision introduced by fast approximate methods for division. An input signal is received and processed to generate a matrix M. The matrix M is inverted to generate an inverted matrix M?1. Matrix M is inverted by (i) decomposing the matrix M into a plurality of first sub-matrices, (ii) generating, based on the first sub-matrices and without any division operations, numerators…
DEFECTIVITY-IMMUNE TECHNIQUE OF IMPLEMENTING MIM-BASED DECOUPLING CAPACITORS
Granted: March 3, 2011
Application Number:
20110051304
An integrated circuit power supply decoupling circuit includes a capacitor and a protection circuit. The capacitor has a first terminal and a second terminal. The protection circuit includes a first transistor having a first conduction path, and a second transistor having a second conduction path. One terminal of the first conduction path is connected to the first terminal of the capacitor, and another terminal of the first conduction path is connected to a first power supply rail. One…
STORAGE SYSTEM DATA COMPRESSION ENHANCEMENT
Granted: March 3, 2011
Application Number:
20110055174
Data segments are logically organized in clusters in a data repository of a data storage system. Each clusters contains compressed data segments and data common to the compression of the segments, such as a dictionary. In association with a write request, it is determined in which of the clusters would the data segment most efficiently be compressed, and the data segment is stored in that data cluster.
METHOD FOR IMPLEMENTING CONTINUOUS DATA PROTECTION UTILIZING ALLOCATE-ON-WRITE SNAPSHOTS
Granted: March 3, 2011
Application Number:
20110055624
The present disclosure is directed to a method for providing continuous data protection for a virtual volume (VV). The method may comprise conceptually dividing the VV into a plurality of same sized chunks; preserving contents of the VV at a specified time; creating a Point in Time (PiT) instance for the VV at the specified time, comprising: a PiT Temporary Virtual Volume (PTVV) for storing modifications to the VV subsequent to the specified time, wherein data stored in the PTVV is…
EFFICIENT POWER MANAGEMENT METHOD IN INTEGRATED CIRCUIT THROUGH A NANOTUBE STRUCTURE
Granted: February 17, 2011
Application Number:
20110039398
Efficient power management method in integrated circuit through a nanotube structure is disclosed. In one embodiment, a method includes patterning a nanotube structure adjacent to a transistor layer of an integrated circuit. The transistor layer may be above a semiconductor substrate. The transistor layer above the semiconductor substrate may comprise a plurality of transistors. The method also includes supplying power to the plurality of transistors through one or more power sources. In…
METHODS AND APPARATUS FOR AUTOMATED PERFORMANCE LIMITING OF AN I/O CONTROL DEVICE
Granted: February 17, 2011
Application Number:
20110040903
Methods and apparatus for configurably limiting performance of an I/O controller device in processing of I/O requests. A performance monitor and control module in the I/O controller device monitors performance of the I/O request processing module and limits its processing to assure that maximum performance threshold values are not exceeded. In one embodiment, the performance monitoring may average performance over one or more periods of time and may provide a moving average window to…
ADAPTIVE FILTERING WITH FLEXIBLE SELECTION OF ALGORITHM COMPLEXITY AND PERFORMANCE
Granted: February 10, 2011
Application Number:
20110033037
An adaptive filter configured to use multiple algorithm species that differ in the quality of echo suppression and respective burdens imposed on the computational resources of the host communication device. Depending on the available computational budget, the adaptive filter selects an algorithm species that, while supporting a relatively high quality of echo suppression, involves a relatively low risk of overwhelming the computational resources. The adaptive filter monitors changes in…
Leakage Power Optimized Structure
Granted: February 3, 2011
Application Number:
20110025393
A digital latch circuit substantially reduces leakage current in output stages of edge-triggered digital switching devices. The circuit comprises first and second NAND gates for receiving first and second input signals and providing first and second output signals. The first NAND gate includes a first A input for receiving the first input signal, a first B input connected to a second NAND gate output, a first leakage current control input connected to a second A input of the second NAND…
METHODS AND APPARATUS FOR METADATA MANAGEMENT IN A STORAGE SYSTEM
Granted: February 3, 2011
Application Number:
20110029580
Methods and systems for metadata management in a storage system are disclosed. First level metadata is associated with a plurality of storage devices in a storage system. Entries in the first level metadata identify storage related attributes of corresponding portions on the plurality of storage devices. Entries in a second level metadata are associated with a corresponding plurality of entries in the first level metadata, where the second level metadata identifies metadata related…
METHODS AND APPARATUS FOR REDUCING INPUT/OUTPUT OPERATIONS IN A RAID STORAGE SYSTEM
Granted: February 3, 2011
Application Number:
20110029728
Methods and systems for managing RAID volumes are disclosed. Metadata is associated with storage devices that comprise a RAID volume. The metadata identifies each of a plurality of portions as being either initialized or non-initialized. The number of I/O operations performed by a storage controller coupled with the storage devices is reduced in response to a request for the RAID volume based on the metadata.
ERASURE CODED DATA STORAGE CAPACITY AND POWER MANAGEMENT
Granted: February 3, 2011
Application Number:
20110029729
A set of data is allocated into a plurality of data chunks, wherein the plurality of data chunks is thinly provisioned and erasure coded. A plurality of storage devices is divided into a first and a second set of storage devices, wherein the first set of storage devices is powered up and the second set of storage devices is powered down. The data chunks are distributed on the first set of storage devices to equally load each of the first set of storage devices. A storage device from the…
METHODS AND APPARATUS FOR POWER ALLOCATION IN A STORAGE SYSTEM
Granted: February 3, 2011
Application Number:
20110029787
Methods and systems for improved management of power allocation among a plurality of devices coupled to a controller. The controller and devices exchange messages to request, grant, and release allocations of power from a common power supply. In some embodiments, the controller may be a SAS/SATA controller and the messages exchanged may be SAS/SATA frames and/or primitives. In exemplary embodiments, the messages may request/grant a particular amount of power for each of one or more…
METHODS AND APPARATUS DYNAMIC MANAGEMENT OF MULTIPLEXED PHYS IN A SERIAL ATTACHED SCSI DOMAIN
Granted: January 27, 2011
Application Number:
20110022736
Methods and systems for automatically, dynamically reconfiguring multiplexing functions of a PHY of a SAS device in response to monitored performance of the PHY and/or in response to changes in configuration of devices in the SAS domain. A SAS device such as a SAS initiator or a SAS expander in a SAS domain may monitor performance of PHYs of the device to detect bandwidth utilization and may reconfigure multiplexing functions of a PHY to improve bandwidth utilization of the PHYs of the…
METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD
Granted: January 27, 2011
Application Number:
20110022998
Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, a method includes: (1) partitioning a design implementation flow for an IC into a late design flow portion and an early design flow portion employing a processor, (2) dividing components of the late design flow portion and the early design flow portion into a functional block implementation section and a top level implementation section employing the processor, (3) aligning dependencies…
