VIRTUAL DATA REPRESENTATION THROUGH SELECTIVE BIDIRECTIONAL TRANSLATION
Granted: January 1, 2009
Application Number:
20090007042
A computer-aided circuit design application has a virtual node feature and a design tool. The virtual node feature is adapted to access design specification information in a first data format and to represent the accessed design specification information as a virtual data node object within a list of node objects in a second data format. The design tool is operable on the list of node objects and the virtual data node object.
POWER MESH FOR MULTIPLE FREQUENCY OPERATION OF SEMICONDUCTOR PRODUCTS
Granted: December 25, 2008
Application Number:
20080320431
The design of integrated circuits, i.e., semiconductor products, is made easier with a semiconductor platform having versatile power mesh that is capable of supporting simultaneous operations having different frequencies on the semiconductor product; e.g., higher frequency operations may be embedded as diffused blocks within the lower layers or may be programmed from a configurable transistor fabric above the diffused layers. Preferably the power mesh is located above the layers having…
APPLICATION OF GATE EDGE LINER TO MAINTAIN GATE LENGTH CD IN A REPLACEMENT GATE TRANSISTOR FLOW
Granted: December 18, 2008
Application Number:
20080308882
A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with…
DIELECTRIC BARRIER FILMS FOR USE AS COPPER BARRIER LAYERS IN SEMICONDUCTOR TRENCH AND VIA STRUCTURES
Granted: December 11, 2008
Application Number:
20080303155
The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent…
METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRCUIT LAYOUT
Granted: November 27, 2008
Application Number:
20080295044
A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second…
Variable Mask Field Exposure
Granted: November 6, 2008
Application Number:
20080274417
A method of fabricating integrated circuits according to a first design. One first pattern is common with a second design, and one second pattern is unique to the first design. The first pattern is imaged using a first mask having first patterns formed in a block thereon. No other patterns of the first and second designs are formed on the first mask. The second patterns are imaged on the substrate using a second mask having second patterns formed in a block thereon. At least one third…
Systems and Methods for Communications Activity Status
Granted: October 23, 2008
Application Number:
20080258908
Various systems and methods for indicating the status of a communication are disclosed herein. For example, status indication methods are disclosed that include initiating a communication that allows for communication between two persons. Further, the methods include determining a combination of status. The combination of status is based on a determination of two or more of the following: a calendar status, a power status, an activity status, and a location status. A communication status…
System and Methods for Copying Digital Information from a Digital Media
Granted: October 23, 2008
Application Number:
20080259479
System and Methods for Copying Digital Information from a Digital Media Various embodiments of the present invention provide systems and methods for copying or ripping digital information contained on one media to another media. In particular, some embodiments of the present invention provide methods and systems for copying digital information contained in a first fixed media onto another media by using digital information content corresponding to that maintained on the first fixed…
LANGUAGE AND TEMPLATES FOR USE IN THE DESIGN OF SEMICONDUCTOR PRODUCTS
Granted: October 23, 2008
Application Number:
20080263480
During the design of semiconductor products which incorporates a user specification and an application set, the application set being a partially manufactured semiconductor platform and its resources, a template engine is disclosed which uses a simplified computer language having a character whereby data used in commands identified by the character need only be input once, either by a user or by files, and that data, after it has been verified to be correct, is automatically allocated to…
ASYMMETRIC ALIGNMENT OF SUBSTRATE INTERCONNECT TO SEMICONDUCTOR DIE
Granted: October 9, 2008
Application Number:
20080248612
An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.
Yield Profile Manipulator
Granted: September 4, 2008
Application Number:
20080216048
A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented,…
TRANSCEIVER WITH FAULT TOLERANT DRIVER
Granted: July 17, 2008
Application Number:
20080170607
A fault tolerant driver circuit includes a data output driver that receives an enable input and that includes a transistor formed on an isolation well. A well bias circuit provides a first well bias to the isolation well. The well bias circuit includes voltage-controlled impedances that are controlled by a voltage of the data output line, the enable input and a supply voltage. The voltage-controlled impedances connect the first well bias alternatively to: a common conductor through a…
PROBABILISTIC NOISE ANALYSIS
Granted: July 3, 2008
Application Number:
20080163145
A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against the voltage threshold, and the victim net design is passed when the probabilistic noise does not exceed the voltage threshold. When the probabilistic noise does exceed the threshold, then an effective noise at a desired mean…
Substrate Laser Marking
Granted: June 12, 2008
Application Number:
20080135981
A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewall angle. A lower sidewall portion of the feature is formed, where the lower sidewall portion forms a void in the substrate. The lower sidewall portion has a lower sidewall angle. The upper sidewall angle of the upper sidewall…
MULTIMODE BLOCK CIPHER ARCHITECTURES
Granted: June 5, 2008
Application Number:
20080130872
An architecture for a block cipher, where the architecture includes functional units that are logically reconfigurable so as to be able to both encrypt clear text into cipher text and decrypt cipher text into clear text using more than one block cipher mode based on at least one of advanced encryption standard and data encryption standard.
Flexible hardware architecture for ECC/HECC based crytography
Granted: June 5, 2008
Application Number:
20080130873
A circuit for implementing elliptic curve and hyperelliptic curve encryption and decryption operations, having a read only memory with no more than about two kilobytes of accessible memory, containing first programming instructions. An arithmetic logic unit has access to second programming instructions that are resident in a gate-level program disposed in the arithmetic logic unit, and is operable to receive data from no more than one input FIFO register. A microcontroller has no more…
MEMORY MAPPING FOR PARALLEL TURBO DECODING
Granted: February 28, 2008
Application Number:
20080049719
A routing multiplexer system provides p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains…
SEMICONDUCTOR DEVICE WITH CONSTRICTED CURRENT PASSAGE
Granted: February 7, 2008
Application Number:
20080032479
A semiconductor device including a gate located over a semiconductor substrate and a source/drain region located adjacent the gate. The source/drain region is bounded by an isolation structure that includes a constricted current passage between the gate and the source/drain region.
VIRTUAL GATEWAY NODE FOR DUAL-MODE WIRELESS PHONES
Granted: November 22, 2007
Application Number:
20070268858
The invention is a virtual gateway that mediates between a dual-mode subscriber device and an IP-based PBX. In particular, the virtual gateway includes a WLAN interface for communicating with the dual-mode subscriber device and a network interface (wired or wireless) for communicating with the IP-based PBX over the Internet. As such, the virtual gateway may relay voice and call control instructions between the dual-mode subscriber device and the IP-based PBX, and may provide the same…
