Synchronous Adaption of Asynchronous Modules
Granted: September 17, 2009
Application Number:
20090235259
A program disposed on a computer readable medium, having a main program with a first routine for issuing commands in an asynchronous manner and a second routine for determining whether the commands have been completed in an asynchronous manner. An auxiliary program adapts the main program to behave in a synchronous manner, by receiving control from the first routine, waiting a specified period of time with a wait routine, passing control to the second routine to determine whether any of…
Stripe Caching and Data Read Ahead
Granted: September 17, 2009
Application Number:
20090235023
A method of improving a serial IO operation, where the serial IO operation includes at least one of a read operation of a data block and a write operation of a data block, and the serial IO operation is directed to a logical disk of a computerized data storage system. Only one stripe of data is read from the logical disk into a cache, and it is determined whether the data block for the IO operation is included within the cache. When the data block for the IO operation is included within…
SIGNAL DELAY SKEW REDUCTION SYSTEM
Granted: July 23, 2009
Application Number:
20090187873
A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding…
SERIAL ADVANCED TECHNOLOGY ATTACHMENT (SATA ) SWITCH
Granted: July 9, 2009
Application Number:
20090177804
An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch.
DUAL PORT SERIAL ADVANCED TECHNOLOGY ATTACHMENT (SATA ) DISK DRIVE
Granted: July 9, 2009
Application Number:
20090177805
An embodiment of the present invention is disclosed to include a hard disk drive allowing for access by two hosts to a device. Further disclosed are embodiments for reducing the delay and complexity of the SATA disk drive.
SWITCHING SERIAL ADVANCED TECHNOLOGY ATTACHMENT (SATA) TO A PARALLEL INTERFACE
Granted: July 9, 2009
Application Number:
20090177815
An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch.
ROUTE AWARE SERIAL ADVANCED TECHNOLOGY ATTACHMENT (SATA ) SWITCH
Granted: July 9, 2009
Application Number:
20090177831
An embodiment of the present invention is disclosed to include a SATA Switch allowing for access by two hosts to a single port SATA device Further disclosed are embodiments for reducing the delay and complexity of the SATA Switch.
MOMENT COMPUTATION ALGORITHMS IN VLSI SYSTEM
Granted: June 18, 2009
Application Number:
20090158228
An improved method for interconnect delay analysis for VLSI circuits reduces a parasitic graph for moment computation by eliminating one or more nodes in the graph. the elimination process is performed based upon the degree of the nodes. By eliminating nodes in this fashion, the computation complexity is significantly reduced. With this elimination process, resistor loops and crossed loops can also be solved. The order in which the nodes are eliminated is optimized using the…
Staged Scenario Generation
Granted: June 4, 2009
Application Number:
20090144679
A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint…
ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS
Granted: May 28, 2009
Application Number:
20090134912
A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value.
COMMAND LANGUAGE FOR MEMORY TESTING
Granted: May 21, 2009
Application Number:
20090133003
A memory testing system for testing a plurality of memory locations in an electronic memory device is provided. The system includes a programmable memory device integrated into the electronic memory device capable of receiving and storing a compiled memory testing program. A processor is in communication with the programmable memory device to read and execute instructions from the compiled testing program stored in the programmable memory device and a command interpreter is configured to…
PHASE JUMP SEQUENCER ARCHITECTURE
Granted: May 7, 2009
Application Number:
20090115483
A method for controlling an output phase of a phase interpolator, by forming an M bit control word, designating N bits of the control word as a fractional number portion, designating M-N bits of the control word as a whole number portion, adjusting a phase jump of the phase interpolator at a designated clock cycle by a first number of phases as designated by the whole number portion plus a second number of phases as designated by the fractional number portion. The designated clock cycle…
TESTING A CIRCUIT WITH COMPRESSED SCAN CHAIN SUBSETS
Granted: April 23, 2009
Application Number:
20090106613
A test system tests a circuit. Compressed scan data subsets are stored, one at a time, in a memory of the test system. The multiple compressed scan data subsets correspond with multiple scan chains in a function block of the tested circuit. Transmission of the compressed scan data subset from the memory to the tested circuit is controlled by the test system. The test system receives a compacted test pattern subset from the tested circuit and provides a test system output that indicates a…
Low Depth Circuit Design
Granted: April 16, 2009
Application Number:
20090100390
A method of designing a logic circuit based on one of the functions of the form fn=x1 (x2 & (x3 (x4 & . . . xn . . . ))) and f?n=x1 & (x2 (x3 & (x4 . . . xn . . . ))), by (a) selecting n as the number of variables of the logic circuit, (b) testing n against a threshold, (c) for values of n less than the threshold, using a first algorithm to design the logic circuit, (d) for values of n greater than the threshold, using a second algorithm to design the logic circuit.
N CELL HEIGHT DECOUPLING CIRCUIT
Granted: February 26, 2009
Application Number:
20090051006
A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with…
PSEUDO LOW VOLUME RETICLE (PLVR) DESIGN FOR ASIC MANUFACTURING
Granted: February 5, 2009
Application Number:
20090034830
A Pseudo Low Volume Reticle (PLVR) which consists of multiple design layers on a single reticle. Specifically, the reticle can include two instances of each layer in order to facilitate die-to-die inspection techniques. A scribe is wrapped around each instance of the layer, such that both the frame and active area of the chip can be inspected with the die-to-die method. The chip consists of design data for a given part. The scribe, or frame, is preferably standard data across products…
INFORMATION SECURITY AND DELIVERY METHOD AND APPARATUS
Granted: February 5, 2009
Application Number:
20090036095
A method includes storing at least one user datum received from a user in a secure storage portion of a memory within a mobile communication device. Authentication information is received into the mobile communication device. The at least one user datum is transmitted from the mobile communication device to a recipient in response to entry of the authentication information, while preventing the user of the mobile communication device from reading the at least one user datum.
JOINT MOSQUITO AND ALIASING NOISE REDUCTION IN VIDEO SIGNALS
Granted: January 29, 2009
Application Number:
20090027548
In one embodiment of the invention, decompressed video signals are upscaled and then filtered using a combined mosquito noise reduction (MNR) and aliasing coring filter that reduces both mosquito noise in the decompressed video signals as well as aliasing noise resulting from the upscaling process. In one implementation, the combined coring filter includes a dual-band filter having two passbands interleaved with two stopbands. The strength of the coring filter may be dynamically…
DISPLAY WITH EFFICIENT MEMORY USAGE
Granted: January 15, 2009
Application Number:
20090015592
A device is capable of displaying an image. The device includes a memory having a first memory portion for receiving a set of image data. A display has a viewport for displaying the set of image data in an image that fits within and fills the viewport. A processor is programmed for executing computer program instructions for receiving a zoom factor selected by a user; applying a zoom transformation to a first subset of the image data corresponding to points in a first region of the image…
Method of Monitoring Commodity Consumption
Granted: January 8, 2009
Application Number:
20090009359
A method and a system for monitoring the quantity of the commodity consumed by a consumer comprises receiving during a preset reporting period window an output value that is security protected from the consumer, extracting a consumption value and a time stamp value from the output value, the extracted values being associated with the quantity, and generating an invoice for the consumer for the quantity of the commodity consumed.
