Methods and structure to assure data integrity in a storage device cache in the presence of intermittent failures of cache memory subsystem
Granted: October 28, 2014
Patent Number:
8874973
Methods and structure for enabling re-training of a DDR memory controller in a storage device without loss of data in the DDR memory devices of the cache memory in response to detecting failure of the memory subsystem during operation of the storage device. In response to detecting a failure of the memory subsystem, the memory controller is reset without resetting the memory devices. The memory controller is then re-trained for operation with the memory device. During the re-training,…
Breaking up long-channel field effect transistor into smaller segments for reliability modeling
Granted: October 28, 2014
Patent Number:
8875070
A first MOS transistor has a channel length. Based on a parameter associated with the first MOS transistor, the first MOS transistor is selected to be simulated as at least a first transistor and a second transistor in series. The circuit is simulated with the first transistor and the second transistor in place of the first MOS transistor. Based on the results of the simulation, device degradations are calculated for the first transistor the second transistor. A degraded netlist is…
Deployment of custom shift array macro cells in automated application specific integrated circuit design flow
Granted: October 28, 2014
Patent Number:
8875071
An automated method is provided for designing an integrated circuit. A net list of an integrated circuit design is generated, wherein the net list includes a scan chain having a sequence of individual scan cells. A sequence of two or more individual scan cells of the scan chain is identified as a candidate for replacement by a custom shift array macro cell. The identified sequence of two or more individual scan cells is then replaced with a custom shift array macro cell that provides a…
System and method of automated design augmentation for efficient hierarchical implementation
Granted: October 28, 2014
Patent Number:
8875079
A hierarchical interface module includes an assessment unit configured to identify a hierarchical implementation incompatibility of an integrated circuit (IC) partitioned block. Additionally, the hierarchical interface module includes an interface unit configured to substitute a directly registered hierarchical interface structure for the hierarchical implementation incompatibility of the IC partitioned block. A method of interfacing hierarchically and a hierarchical implementation…
Thread synchronization in a multi-thread, multi-flow network communications processor architecture
Granted: October 28, 2014
Patent Number:
8874878
Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from processing modules of the network processor. The packet classifier processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler, and each thread associated with a data flow. A…
Methods and structure for hardware management of serial advanced technology attachment (SATA) DMA Non-Zero Offsets in a serial attached SCSI (SAS) expander
Granted: October 21, 2014
Patent Number:
8868806
Methods and structure for enhanced SAS expander functionality to store and forward buffered information transmitted from a SATA end device to an STP initiator device while managing use of Non-Zero Offset (“NZO”) field values in DMA Setup FISs transmitted by the SATA end device. The enhanced expander establishes a connection between an STP initiator and a SATA end device. The expander forwards a read command from the initiator to the end device. If NZO use is supported and enabled in…
Speculative task reading in a traffic manager of a network processor
Granted: October 21, 2014
Patent Number:
8869156
Described embodiments provide for scheduling packets for transmission by a network processor. The network processor generates tasks corresponding to received packets associated with a data flow. A traffic manager of the network processor receives tasks provided by a processing module of the network processor and generates a tree scheduling hierarchy having one or more scheduling levels. Each received task is queued in a queue of the scheduling hierarchy associated with the received task,…
Packet draining from a scheduling hierarchy in a traffic manager of a network processor
Granted: October 21, 2014
Patent Number:
8869151
Described embodiments provide for controlling a state of each node in a scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. A traffic manager enqueues received tasks in a queue of the scheduling hierarchy associated with a data flow. The traffic manager maintains scheduling data structures for each node in the scheduling…
Local messaging in a scheduling hierarchy in a traffic manager of a network processor
Granted: October 21, 2014
Patent Number:
8869150
Described embodiments provide for queuing tasks in a scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The traffic manager performs a task enqueue operation for the task. The task enqueue operation includes adding the received task to an associated queue of the scheduling hierarchy, where the queue is associated with a…
Object code configuration tool
Granted: October 21, 2014
Patent Number:
8869104
A system and method for managing several versions of a device with embedded object code by using an editor to scan the object code, find a signature, change one or more parameters within the object code, and replace the object code. The device may be shipped to a customer in a standard configuration and the object code may be changed by the customer using the editor.
Instruction breakpoints in a multi-core, multi-thread network communications processor architecture
Granted: October 21, 2014
Patent Number:
8868889
Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate threads of contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes instructions corresponding to threads received from the scheduler. The multi-thread instruction engine executes…
Systems and methods for handling out of order reporting in a storage device
Granted: October 21, 2014
Patent Number:
8868854
Various embodiments of the present invention provide systems and methods for handling out of order reporting in a storage device.
Interrupt queuing in a media controller architecture
Granted: October 21, 2014
Patent Number:
8868809
Described embodiments provide a media controller for servicing contexts corresponding to data transfer requests from host devices. The media controller includes a context generator for generating contexts corresponding to the data transfer requests and a buffer for storing one or more context pointers, each pointer corresponding to a context and an action by a system module associated with the context. A context processor is configured to complete a context when the action by a media…
Scatter gather list for data integrity
Granted: October 21, 2014
Patent Number:
8868517
A system and method for improving message passing between a computer and peripheral devices is disclosed. The system and method for improving message passing between a computer and peripheral devices incorporate data checking on the command/message data and each scatter gather list element. The method in accordance with the present disclosure enables a peripheral device to check the integrity of the message and ownership of the scatter gather list element before the data is processed.
Systems and methods for data processing using soft data shaping
Granted: October 21, 2014
Patent Number:
8868475
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for manipulating soft data in a data processing system.
Pre and post-acquisition tap quantization adjustment in decision feedback equalizer
Granted: October 21, 2014
Patent Number:
8867602
A tap coefficient control circuit and a method for controlling a tap coefficient for a decision feedback equalizer are disclosed. The method includes adjusting a correction voltage applied to the tap coefficient based on a first tap quantization and detecting a decision feedback equalizer tap convergence. After the decision feedback equalizer tap convergence is detected, the method adjusts the correction voltage applied to the tap coefficient based on a second tap quantization, wherein…
Systems and methods for P-distance based priority data processing
Granted: October 21, 2014
Patent Number:
8867156
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.
Systems and methods for processing data with linear phase noise predictive filter
Granted: October 21, 2014
Patent Number:
8867154
Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for data processing with a linear phase noise predictive filter. A data processing system includes an equalizer circuit operable to filter a digital data input to yield equalized data, a linear phase noise predictive finite impulse response filter operable to filter the equalized data to yield filtered data, and a data detector circuit operable to apply a data detection algorithm to the…
Symbol selective scaling with parity forcing
Granted: October 14, 2014
Patent Number:
8862957
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing.
Systems and methods for parity shared data encoding
Granted: October 14, 2014
Patent Number:
8862960
Various embodiments of the present invention provide systems and methods for data processing. For example, a low density parity check encoding system is described that includes: a low density parity check encoder circuit, and a combining circuit. The low density parity check encoder circuit is operable to encode a first data set to yield a first low density parity check encoded sub-codeword, and to encode a second data set to yield a second low density parity check encoded sub-codeword.…
