Sector failure prediction method and related system
Granted: November 11, 2014
Patent Number:
8886991
A method and system is disclosed for identification and removal of a memory sector prone to failure. The method performs satisfaction checks on the memory sector and monitors and stores returned Unsatisfied Checks (USC) for analysis by a pattern recognition algorithm. Once a first global iteration is pattern matched with a second global iteration from the sector, the method determines the period of the repetitive pattern. The method then identifies, as the sector prone to failure, the…
Methods and apparatus for reusing snoop responses and data phase results in a bus controller
Granted: November 11, 2014
Patent Number:
8886889
Methods and apparatus are provided for reusing snoop responses and data phase results in a bus controller. A bus controller receives an incoming bus transaction BTR1 corresponding to an incoming cache transaction CTR1 for an entry in at least one cache; issues a snoop request with a cache line address of the incoming bus transaction BTR1 for the entry to a plurality of cache controllers; collects at least one snoop response from the plurality of cache controllers; broadcasts a combined…
Systems and methods for shared layer data decoding
Granted: November 11, 2014
Patent Number:
8885276
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.
Systems and methods for improved data detection processing
Granted: November 4, 2014
Patent Number:
8880986
The present invention is related to systems and methods for enhancing data detection in a data processing system. In one embodiment, a data processing system is disclosed that includes a data detector circuit that is governed at least in part based upon selected coefficients. The selected coefficients are selected as either a first set of coefficients or a second set of coefficients where the second set of coefficients has fewer coefficients than the first set of coefficients.
I/O control, synchronization method in a raid environment with co-existing hardware and software-based I/O paths
Granted: November 4, 2014
Patent Number:
8880802
The present invention is directed to a command block protocol which may implemented by RAID firmware for synchronizing I/Os in a RAID system which includes co-existing hardware and software-based I/O paths. The command block protocol of the present disclosure ensures that there aren't any I/Os outstanding in the fast path or any other hardware engine by making sure that the region lock (ex.—Sentinel Region Lock) is taken for the entire size of the volume. When the Sentinel Region Lock…
Hardware independent simple network management protocol based on a generic data collection scheme
Granted: November 4, 2014
Patent Number:
8880578
A method and/or a system for a generic agent in a managed network are disclosed. In one embodiment, a method of a generic simple network management protocol (SNMP) module on a network node includes communicating with a device succeedingly coupled to the network node using a data collector module assigned to the device. The method also includes translating data passed between the device and a management module managing the device based on a simple network management protocol.
Compensation loop for read voltage adaptation
Granted: November 4, 2014
Patent Number:
8879324
The disclosure is directed to a system and method for nominal read voltage variations of a flash device. N reads are performed, each at a selected voltage offset from an initial read voltage. An N bit digital pattern associated with the selected voltage offsets is generated for the N reads. The N bit digital pattern generated by the N reads is mapped to a signed representation. A voltage adjustment based upon the signed representation is applied to at least partially compensate for a…
Pre-charge tracking of global read lines in high speed SRAM
Granted: November 4, 2014
Patent Number:
8879303
In embodiments of the invention, a memory circuit includes a static random access memory (SRAM), rows of M sense amplifiers, a global read precharge tracking control circuit controlling a precharge of global read lines, a sense amplifier output tracking circuit generating a reset sense amplifier signal for the sense amplifier control circuits, and a read delay circuit generating a trigger signal for the global read precharge tracking control circuit and the sense amplifier output…
Storage media inter-track interference cancellation
Granted: November 4, 2014
Patent Number:
8879182
Described embodiments provide a method of cancelling inter-track interference (ITI) from one or more sectors read from a desired track of a storage medium. A road channel reads sectors in a desired track of the storage medium. A decoder of the read channel decodes the read sectors, and if the read sectors are incorrectly recovered from the storage medium, selected sectors of a first adjacent track and a second adjacent track are read. An ITI canceller of the read channel estimates ITI in…
System and method of automated design augmentation for efficient hierarchical implementation
Granted: October 28, 2014
Patent Number:
8875079
A hierarchical interface module includes an assessment unit configured to identify a hierarchical implementation incompatibility of an integrated circuit (IC) partitioned block. Additionally, the hierarchical interface module includes an interface unit configured to substitute a directly registered hierarchical interface structure for the hierarchical implementation incompatibility of the IC partitioned block. A method of interfacing hierarchically and a hierarchical implementation…
Sampling-phase acquisition based on channel-impulse-response estimation
Granted: October 28, 2014
Patent Number:
8873180
Embodiments of the invention can be manifested as methods for converting analog waveforms into digital sampled signals. In at least one such embodiment, the method includes (i) sampling, based on a sampling-clock signal, an analog waveform received from a transmission channel to generate a digital sampled signal, (ii) generating a digital target signal by applying a specified reference data pattern to a model of the transmission channel, and (iii) adjusting the sampling-clock signal by…
Deployment of custom shift array macro cells in automated application specific integrated circuit design flow
Granted: October 28, 2014
Patent Number:
8875071
An automated method is provided for designing an integrated circuit. A net list of an integrated circuit design is generated, wherein the net list includes a scan chain having a sequence of individual scan cells. A sequence of two or more individual scan cells of the scan chain is identified as a candidate for replacement by a custom shift array macro cell. The identified sequence of two or more individual scan cells is then replaced with a custom shift array macro cell that provides a…
Breaking up long-channel field effect transistor into smaller segments for reliability modeling
Granted: October 28, 2014
Patent Number:
8875070
A first MOS transistor has a channel length. Based on a parameter associated with the first MOS transistor, the first MOS transistor is selected to be simulated as at least a first transistor and a second transistor in series. The circuit is simulated with the first transistor and the second transistor in place of the first MOS transistor. Based on the results of the simulation, device degradations are calculated for the first transistor the second transistor. A degraded netlist is…
Methods and structure to assure data integrity in a storage device cache in the presence of intermittent failures of cache memory subsystem
Granted: October 28, 2014
Patent Number:
8874973
Methods and structure for enabling re-training of a DDR memory controller in a storage device without loss of data in the DDR memory devices of the cache memory in response to detecting failure of the memory subsystem during operation of the storage device. In response to detecting a failure of the memory subsystem, the memory controller is reset without resetting the memory devices. The memory controller is then re-trained for operation with the memory device. During the re-training,…
Thread synchronization in a multi-thread, multi-flow network communications processor architecture
Granted: October 28, 2014
Patent Number:
8874878
Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from processing modules of the network processor. The packet classifier processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler, and each thread associated with a data flow. A…
Identification and containment of performance hot-spots in virtual volumes
Granted: October 28, 2014
Patent Number:
8874867
A method includes provisioning a virtual volume from at least one storage pool of a storage array, designating at least one virtual volume segment of the virtual volume for mapping a virtual volume range to a virtual drive range, organizing the virtual volume range into a plurality of clusters, measuring a data load on each of the plurality of clusters and comparing the data load on each of the plurality of clusters to activity of the virtual volume, and reconfiguring the at least one…
Determining coefficients for digital low pass filter given cutoff and boost values for corresponding analog version
Granted: October 28, 2014
Patent Number:
8874633
Methods and apparatus are provided for determining coefficients for a digital low pass filter, given cutoff and boost values for a corresponding analog version of the digital low pass filter. Coefficients are determined for a digital low pass filter by obtaining cutoff and boost values for a corresponding analog version of the digital low pass filter; and determining the coefficients for the digital low pass filter based on the obtained cutoff and boost values. The coefficients can be…
Task queuing in a multi-flow network processor architecture
Granted: October 28, 2014
Patent Number:
8873550
Described embodiments generate tasks corresponding to each packet received by a network processor. A destination processing module receives a task and determines, based on the task size, a queue in which to store the task, and whether the task is larger than space available within a current memory block of the queue. If the task is larger, an address of a next memory block in a memory is determined, and the address is provided to a source processing module of the task. The source…
Touchdown detection in magnetic disk storage devices
Granted: October 28, 2014
Patent Number:
8873194
Touchdown detection in magnetic storage devices is provided to detect contact between a storage medium and a magnetic head having an embedded contact sensor. A sample stream is obtained, which includes samples of a sensor signal output from the embedded contact sensor. The sample stream is segmented into multiple segments. A modulation depth is determined for each of the segments. A combined modulation depth is determined by combining the modulation depths of the segments using a…
Multi-path data processing system
Granted: October 28, 2014
Patent Number:
8873182
Various embodiments of the present invention provide apparatuses and methods for processing data in a multi-path data processing circuit. For example, an apparatus is disclosed that includes a first filter operable to process a first digital data stream to yield a first filtered digital data stream, a second filter operable to process a second digital data stream to yield a second filtered digital data stream, wherein the first and second digital data stream are representative of a same…
