Methods and structure for normalizing storage performance across a plurality of logical volumes
Granted: April 28, 2015
Patent Number:
9021199
Methods and structure are disclosed for normalizing storage performance across a plurality of logical volumes. One embodiment is a storage controller. The storage controller is adapted to couple with a plurality of host systems and a storage device. The storage controller is adapted to receive one or more requests to create logical volumes for the plurality of hose systems, and adapted to identify a plurality of performance zones for storage areas of the storage device. The performance…
Server direct attached storage shared through physical SAS expanders
Granted: April 28, 2015
Patent Number:
9021166
A system and method for servers to belong to a cascaded cluster of nodes (or servers) is disclosed. Servers share storage in common without the need of an external element such as a switch and or external storage device. SAS technology is used with direct attached drives in each node, and connections between each node, to emulate a SAN environment through a cascaded SAS topology. SAS HBAs each containing an SAS expander, connect elements internal to each server with elements external to…
Apparatus and systems having storage devices in a side accessible drive sled
Granted: April 28, 2015
Patent Number:
9019708
Apparatus and systems for improved access to storage devices from the sides of sleds mounted in storage enclosures. Embodiments provide apparatus and systems for a sled in a storage enclosure that provides access to storage devices on either side of the sled when the sled is slid forward out of its enclosure. Multiple sleds may be enclosed within a single enclosure to permit access to a portion of the storage devices in the enclosure hence reducing the problems of instability of the rack…
Band-pass high-order analog filter backed hybrid receiver equalization
Granted: April 21, 2015
Patent Number:
9014252
A channel equalization scheme is provided. A linear equalizer using a continuous-time linear equalization and a decision feedback equalizer using a discrete-time decision feedback equalization are integrated together from a hybrid receiver equalizer. The continuous-time linear equalization scheme and the discrete-time decision feedback equalization scheme are blended using a joint adaptation algorithm to form an equalization scheme for inter-symbol interference cancellation in the hybrid…
Low density parity check layer decoder for codes with overlapped circulants
Granted: April 21, 2015
Patent Number:
9015550
The present inventions are related to systems and methods for decoding data in an LDPC layer decoder for LDPC codes with overlapped circulants.
Multi-level LDPC layered decoder with out-of-order processing
Granted: April 21, 2015
Patent Number:
9015547
An apparatus for low density parity check decoding includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node messages and to calculate checksums based on the variable node to check node messages, and a scheduler operable to determine a layer processing order for the variable node processor and the…
Smart active-active high availability DAS systems
Granted: April 21, 2015
Patent Number:
9015525
A high availability DAS system uses a solid state cache to provide near active-active performance in a DAS duster, while retaining the implementation simplicity of active-passive or dual active system. Each node in the duster may include a solid state cache that stores hot I/O in an active-active mode, which allows the data to be read from or written to the underlying dual-active or active/passive DAS RAID system only when access to the “hot Region” cools down or in the case of Cache…
Self-sizing dynamic cache for virtualized environments
Granted: April 21, 2015
Patent Number:
9015418
A method and system for self-sizing dynamic cache for virtualized environments is disclosed. The preferred embodiment self sizes unequal portions of the total amount of cache and allocates to a plurality of active virtualized machines (VM) according to VM requirements and administrative standards. As a new VM may emerge and request an amount of cache, the cache controller reclaims currently used cache from the active VM and reallocates the unequal portions of cache required by each VM.…
Methods and structure for identifying support for super-standard features in communications between serial attached SCSI devices
Granted: April 21, 2015
Patent Number:
9015398
Methods and structure for determining compatibility between a pair of SAS devices for support of super-standard features of the devices. Features and aspects hereof provide for exchange of information between a first and second SAS device using SAS protocol in non-standard manners. The exchanges are designed to exchange information between compatible, enhanced device without causing protocol violation errors in either the first or second devices. The information exchanged represents…
Error signature analysis for data and clock recovery in a communication system
Granted: April 21, 2015
Patent Number:
9014313
Described embodiments recover timing and data information from a signal received via a communication channel. An analog-to-digital converter (ADC) operating at a baud rate of the communication channel generates an actual ADC value corresponding to each bit sample of the received signal. A fast symbol estimation module estimates, based on the actual ADC value, a bit value corresponding to each bit sample. The fast symbol estimation module operates at a digital clock rate. The estimated…
Adaptive pattern detection for pattern-dependent write current control in a magnetic recording system
Granted: April 21, 2015
Patent Number:
9013816
The disclosure is directed to a system and method of a system and method for determining fundamental bit cell duration of a data record, which can be used for pattern-dependent write (PDW) current control. According to various embodiments of the disclosure, at least a first portion of a data record is fed through a plurality of delay units. A binary output of each delay unit is stored in at least one register when the delay units have received the first portion of the data record. The…
Systems and methods for reusing a layered decoder to yield a non-layered result
Granted: April 14, 2015
Patent Number:
9009557
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.
Adjustment of data storage capacity provided by a storage system
Granted: April 14, 2015
Patent Number:
9009440
A storage system stores data in at least one partition of a physical storage media in accordance with file system information specifying a plurality of logical blocks having logical block addresses within the partition. The logical blocks include excess logical blocks that are not mapped to space in the physical storage media by the mapping employed by the storage system. Unusable block data marks those excess logical blocks as unusable. This makes it easy to adjust the data storage…
Methods and systems for instantaneous online capacity expansion
Granted: April 14, 2015
Patent Number:
9009405
The disclosure provides instantaneous, vertical online capacity expansion (OCE) for redundant (e.g., RAID-5, RAID-6) and non-redundant (e.g., RAID-0) arrays. The new OCE technique implements vertical expansion instead of the horizontal expansion techniques implemented in current OCE techniques. The vertical expansion treats any new addition of storage as an extension of the capacity of the preexisting physical drives in order to avoid having to rewrite the data blocks of the original,…
Sharing of bypassed I/O transaction information
Granted: April 14, 2015
Patent Number:
9009375
A first I/O transaction request is sent to a storage controller for processing by firmware running on the storage controller. A second I/O transaction request is sent to storage hardware without further processing by the firmware running on the storage controller. Since the firmware did not process the second I/O transaction request, information associated with the second I/O transaction is stored in in a circular buffer accessible to the firmware running on the storage controller. The…
Intelligent data buffering between interfaces
Granted: April 14, 2015
Patent Number:
9009370
A dynamically controllable buffering system includes a data buffer that is communicatively coupled between first and second data interfaces and operable to perform as an elasticity first-in-first-out buffer in a first mode and to perform as a store-and-forward buffer in a second mode. The system also includes a controller that is operable to detect data rates of the first and second data interfaces, to operate the data buffer in the first mode when the first data interface has a data…
Methods and structure for reduced layout congestion in a serial attached SCSI expander
Granted: April 14, 2015
Patent Number:
9007943
Methods and structure for reduced layout congestion in a switching device integrated circuit. A switching device such as a Serial Attached SCSI (SAS) expander comprises a switching circuit to couple any of a plurality (“N”) of physical links of the switching device with any other physical link of the switching device. The switching circuit comprises a first stage circuit adapted to couple any of the N physical links with a selected one of N/2 communication paths of the switching…
Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding
Granted: April 14, 2015
Patent Number:
9007828
Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline…
Multiple sync mark storage system
Granted: April 7, 2015
Patent Number:
9001445
A data processing system includes a number of analog to digital converters operable to sample analog signals obtained from a magnetic storage medium to yield digital signals, multiple sync mark detectors operable to search for a number of different sync marks in the digital signals, and a sync mark detector output comparator operable to compare an output of each of the sync mark detectors to identify detection errors.
System and method for power saving modes in multi-sensor magnetic recording
Granted: April 7, 2015
Patent Number:
9001446
A system and method for power management in a hard disk drive (HDD) assembly incorporating two or more read sensors includes directing a read/write head to follow a track; depowering one or more read sensors and readpath circuits associated with the read sensors; reading an analog readback signal through the first read sensor; processing the signal through an analog front-end to generate an input signal; sampling the input signal through an analog to digital converter at a first…
