Multiple sync mark storage system
Granted: April 7, 2015
Patent Number:
9001445
A data processing system includes a number of analog to digital converters operable to sample analog signals obtained from a magnetic storage medium to yield digital signals, multiple sync mark detectors operable to search for a number of different sync marks in the digital signals, and a sync mark detector output comparator operable to compare an output of each of the sync mark detectors to identify detection errors.
LDPC decoder trapping set identification
Granted: March 31, 2015
Patent Number:
8996971
The present inventions are related to systems and methods for detecting trapping sets in LDPC decoders, and particularly for detecting variable nodes in trapping sets in a non-erasure channel LDPC decoder.
Systems and methods for positive feedback short media defect detection
Granted: March 31, 2015
Patent Number:
8996970
Various systems and methods for media defect detection.
Low density parity check decoder with miscorrection handling
Granted: March 31, 2015
Patent Number:
8996969
A data processing system includes a decoder circuit, syndrome calculation circuit and hash calculation circuit. The decoder circuit is operable to apply a decoding algorithm to a decoder input based on a first portion of a composite matrix to yield a codeword. The syndrome calculation circuit is operable to calculate a syndrome based on the codeword and on the first portion of the composite matrix. The hash calculation circuit is operable to calculate a hash based on a second portion of…
Providing multi-initiator serial advanced technology attachment support in a multi-initiator environment
Granted: March 31, 2015
Patent Number:
8996748
A storage system and method for preventing propagation of link reset among initiators in the storage system is disclosed. The method includes issuing a link reset command by the initiator, and entering the initiator into a back-off period immediately following the issuing of the link reset command. The initiator remains idle for the entire duration of the back-off period and resumes its operations at the end of the back-off period.
Nyquist constrained digital finite impulse response filter
Granted: March 31, 2015
Patent Number:
8996597
Various embodiments of the present invention provide apparatuses and methods for filtering a digital signal with a Nyquist constrained digital finite impulse response filter. For example, an apparatus for filtering digital data is disclosed that includes a digital finite impulse response filter having a plurality of taps. The apparatus also includes a tap weight controller connected to the digital finite impulse response filter, operable to adjust a tap weight for each of a subset of the…
Method and apparatus for high density pulse density modulation
Granted: March 31, 2015
Patent Number:
8995521
A method and system for high density pulse density modulation is disclosed. In accordance with the present disclosure, a modulation function is split in to two band limited streams using a complementary pair of non-linear functions. More specifically, one bitstream definition contains the peaks of the original function while the other bitstream contains a soft clipping version of the original bitstream. The bitstreams are applied to a pair of switching amplifiers, and the bitstreams can…
Servo system with signal to noise ratio marginalization
Granted: March 31, 2015
Patent Number:
8995072
A servo system includes a detector circuit operable to apply a data detection algorithm to digital data to yield hard decisions, a convolution circuit operable to yield ideal digital data based on the hard decisions and on target values, a subtraction circuit operable to subtract the ideal digital data from the digital data to yield an error signal, a scaling circuit operable to scale the error signal to yield a scaled noise signal, an adder operable to add the scaled noise signal to the…
Circuit and method for dynamically changing a trip point in a sensing inverter
Granted: March 24, 2015
Patent Number:
8988959
A circuit and method for dynamically changing trip point voltage in a sensing inverter circuit. In one embodiment, the sensing inverter circuit includes: (1) a base inverter circuit couplable to logic-high and logic-low voltage sources at respective inputs thereof and configured to transition an output thereof from a previous logic-level voltage to a present logic-level voltage based on a logic value of an input voltage received by the base inverter circuit, and (2) a feedback circuit…
Smart discovery model in a serial attached small computer system topology
Granted: March 24, 2015
Patent Number:
8990448
Methods, systems and processor-readable media are disclosed for implementing a “smart” discovery process in a data transfer regime having one or more expanders and one or more initiators. Data traffic associated with such a discovery process can be reduced and one or more of the initiators can be prevented from blocking input/output to particular components in communication with the data transfer regime, thereby improving and completing the discovery process in an optimal time frame…
Method of fabrication of through-substrate vias
Granted: March 24, 2015
Patent Number:
8987137
A method of manufacturing a through-substrate-via structure. The method comprises providing a substrate having a front-side and an opposite back-side. A through-substrate via opening is formed in the front-side of the substrate. The through-substrate-via opening does not penetrate an outer surface of the back-side of the substrate. The through-substrate-via opening is filled with a solid fill material. Portions of the substrate from the outer surface of the back-side of the substrate are…
Subtractive validation of cache lines for virtual machines
Granted: March 17, 2015
Patent Number:
8984234
A method and system for managing a cache for a host machine is disclosed. The method includes: indicating each cache line in the cache as being in a transitional meta-state when any virtual machine hosted on the host machine moves out of the host machine; each time a particular cache line is accessed, indicating that particular cache line as no longer in the transitional meta-state; and marking the cache lines still in the transitional meta-state as invalid when a virtual machine moves…
Methods and structure for task management in storage controllers of a clustered storage system
Granted: March 17, 2015
Patent Number:
8984222
Methods and structure for task management in storage controllers of a clustered storage system. An initiator storage controller of the clustered storage system ships I/O requests for processing to a target storage controller of the system. Responsive to a need to abort a previously shipped I/O request, the initiator storage controller transmits a task management message to the target storage controller. The task management message identifies one or more previously shipped I/O requests to…
Method and apparatus for access point selection using channel correlation in a wireless communication system
Granted: March 17, 2015
Patent Number:
8983467
A method and apparatus are provided for access point selection in wireless communication systems, such as wireless LANs. A disclosed wireless communication device includes a roaming process that selects an access point based on a measure of correlation on a channel to one or more surrounding access points. The roaming process selects an access point, for example, having the lowest correlation value. The roaming process may also consider the signal quality, channel delay spread or both in…
Block-based crest factor reduction (CFR)
Granted: March 17, 2015
Patent Number:
8982992
Block-based crest factor reduction (CFR) techniques are provided. An exemplary block-based crest factor reduction method comprises obtaining a block of data samples comprised of a plurality of samples; applying the block of data to a crest factor reduction block; and providing a processed block of data from the crest factor reduction block. The block-based crest factor reduction method can optionally be iteratively performed a plurality of times for the block of data. The block of data…
Predictive selection in a fully unrolled decision feedback equalizer
Granted: March 17, 2015
Patent Number:
8982941
Described embodiments provide a non-uniformly quantized analog-to-digital converter (ADC) for generating a value for each sample of a received signal. The ADC includes arrays of decision comparators provided the received signal. Each comparator has a threshold voltage set according to a corresponding bit history of a predictive decision feedback equalizer (DFE), and each bit history is associated with a tap of the DFE. Each comparator provides a bit value based on the corresponding bit…
Multi-layer integrated transmission line circuits having a metal routing layer that reduces dielectric losses
Granted: March 17, 2015
Patent Number:
8981864
Multi-layer in integrated transmission line circuits are provided having improved signal loss characteristics. A multi-layer integrated transmission line circuit, such as a stripline circuit or a microstrip circuit, comprises at least one reference layer; at least one conducting layer having one or more conducting strips, wherein the at least one conducting layer is separated from the at least one reference layer by a substrate; and at least one additional layer positioned between the at…
System and method for generating soft-orthogonal syncmarks
Granted: March 10, 2015
Patent Number:
8976477
The disclosure is directed to a system and method of generating soft-orthogonal syncmarks for at least a first set of tracks and a second set of tracks. Random pairs of sync patterns are searched to identify one or more pairs where the sync patterns of each pair exhibit delta-like autocorrelation and small cross-correlation with each other and with preamble portions of the tracks. Then a pair of sync patterns is selected from the one or more identified pairs, where the selected pair…
Communications system supporting multiple sector sizes
Granted: March 10, 2015
Patent Number:
8976876
In one embodiment, a configurable communications system accommodates a plurality of different transmission word sizes. In a transmit path, the system inserts a number of padding bits corresponding to missing user-data bits onto the end of an input data sequence to generate a set of data having N bits. The N bits are interleaved and error-correction (EC) encoded to generate parity bits corresponding to an EC codeword. The parity bits are de-interleaved and multiplexed with the input data…
Time synchronization using packet-layer and physical-layer protocols
Granted: March 10, 2015
Patent Number:
8976778
In certain embodiments, a slave clock node in a wireless packet network achieves time synchronization with a master clock node by implementing a packet-layer synchronization procedure, such as the IEEE1588 precision timing protocol (PTP), to set the slave's local time based on the master's time. The slave's local time is then maintained by implementing a physical-layer syntonization procedure, such as synchronous Ethernet, without relying on the packet-layer synchronization procedure.…
