Method and apparatus for communicating orthogonal pilot tones in a multiple antenna communication system
Granted: February 24, 2015
Patent Number:
8964522
Methods and apparatus are provided for communicating pseudo-orthogonal pilot tones in a multiple antenna communication system. Data is transmitted in a multiple antenna communication system having N transmit antennas by generating a number of pilot tones for each of the N transmit antennas, wherein the pilot tones for each of the N transmit antennas are pseudo-orthogonal with each other; and transmitting the data on each of the N transmit antennas. The pilot tones are generally embedded…
Semiconductor structure with waveguide
Granted: February 24, 2015
Patent Number:
8960969
A light-emitting diode (LED) apparatus comprises a substrate, a first layer formed over at least a portion of the substrate, an active layer formed over at least a portion of the first layer, a second layer formed over at least a portion of the active layer, and at least one waveguide formed below the substrate. A first portion of light from the LED is directed in a first direction and a second portion of light from the LED is directed in a second direction via the waveguide, the second…
Structural rule analysis with TCL scripts in synthesis or STA tools and integrated circuit design tools
Granted: February 17, 2015
Patent Number:
8959467
A method of designing a circuit, an apparatus and a structural analysis tool are disclosed. In one embodiment, the structural analysis tool includes: (1) a structural analyzer configured to apply a structural rule to the circuit design in a design environment of said design process having valid timing data and (2) a structural assessor configured to generate structural data of the circuit design based on application of the structural rule by the structural analyzer.
Systems and methods for hybrid layer data decoding
Granted: February 17, 2015
Patent Number:
8959414
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.
Two-port memory capable of simultaneous read and write
Granted: February 17, 2015
Patent Number:
8959291
Described embodiments provide a multi-port memory system that has a plurality of memory banks and an equal number of mapping memory banks, each one of the data memory banks corresponding to one of the mapping memory banks. The multi-port memory reads, from one of the mapping memory banks selected by a read logical bank number, a read physical bank number identifying which one of the data memory banks data is to be read. The memory system also calculates, from at least one physical bank…
Methods and apparatus for reusing snoop responses and data phase results in a cache controller
Granted: February 17, 2015
Patent Number:
8959290
Methods and apparatus are provided for reusing snoop responses and data phase results in a cache controller. A cache controller receives a broadcast combined snoop response from a bus controller, wherein the broadcast combined snoop response corresponds to an incoming bus transaction BTR1 corresponding to a cache transaction CTR1 for an entry in at least one cache and wherein the combined snoop response is a combination of at least one snoop response from a plurality of cache…
SerDes jitter tolerance BIST in production loopback testing with enhanced spread spectrum clock generation circuit
Granted: February 17, 2015
Patent Number:
8958515
A system for controllably generating jitter in a serial data stream includes a frequency generator and first and second mixers. The frequency generator is configured to output in-phase and quadrature local oscillator signals with a local oscillator frequency of at least about 5 MHz. The local oscillator frequency varies between a selectable minimum frequency and a selectable maximum frequency. The first mixer is configured to mix a fixed frequency clock signal with the in-phase local…
Method and system for sliding-window based phase, gain, frequency and DC offset estimation for servo channel
Granted: February 17, 2015
Patent Number:
8958166
Sliding-window based data processing includes receiving an analog signal, converting the analog signal to a series of digital samples synchronous to a sampling clock, performing a first discrete Fourier transform on a first portion of the series of digital samples, performing a second discrete Fourier transform on a second portion of the series of digital samples, performing a third discrete Fourier transform on a third portion of the series of digital samples, generating a first series…
Pattern-based loss of signal detector
Granted: February 10, 2015
Patent Number:
8953665
In described embodiments, data pattern-based detection of loss of signal (LOS) is employed for a receive path of serializer/deserializer (SerDes) devices. Pattern-based LOS detection allows for detection of data loss over variety of types of connection media, and is generally insensitive to signal attenuation. More specifically, some described embodiments disclose reliable pattern-based detection of LOS across different connection media for incoming receive data when discreet time…
Methods and structure for single root input/output virtualization enhancement in peripheral component interconnect express systems
Granted: February 10, 2015
Patent Number:
8954788
In one embodiment, a Peripheral Component Interconnect Express (PCIe) Input/Output (I/O) device operable to perform Single Root I/O Virtualization (SR-IOV) is provided. The device comprises hardware registers implementing a PCIe configuration space for the device, and firmware implementing one or more SR-IOV virtual functions that each provide a virtual machine access to a subset of PCIe configuration space hardware registers for the device. The device further includes a hardware…
Flash memory read retry using histograms
Granted: February 10, 2015
Patent Number:
8953373
Upon a read error, a flash memory controller adjusts a candidate reference voltage on successive read retries until either a read error no longer occurs or an optimal reference voltage is attained. Optimal reference voltages correspond to cross-points of flash memory cell voltage distributions. Cross-points can be determined by using different candidate reference voltages to read data from the memory and determining corresponding decision patterns. The frequency of occurrence of the…
Digital input detector and associated adaptive power supply
Granted: February 10, 2015
Patent Number:
8953267
Interface circuitry of a storage device or other type of processing device comprises a digital input detector and an adaptive power supply. The digital input detector comprises an input transistor. The adaptive power supply provides a variable supply voltage to the digital input detector that varies with a threshold voltage of the input transistor. In one embodiment, the variable supply voltage provided to the digital input detector by the adaptive power supply varies with the threshold…
Thermal improvement of integrated circuit packages
Granted: February 3, 2015
Patent Number:
8946871
An integrated circuit package comprising an active semiconductor device layer and at least one heat-transfer semiconductor layer on the active semiconductor device layer. The heat-transfer semiconductor layer has a coefficient of thermal expansion that substantially matches a coefficient of thermal expansion of the active semiconductor device layer.
Multi-threaded processing with hardware accelerators
Granted: February 3, 2015
Patent Number:
8949838
Described embodiments process multiple threads of commands in a network processor. One or more tasks are generated corresponding to each received packet, and the tasks are provided to a packet processor module (MPP). A scheduler associates each received task with a command flow. A thread updater writes state data corresponding to the flow to a context memory. The scheduler determines an order of processing of the command flows. When a processing thread of a multi-thread processor is…
High density disk drive performance enhancement system
Granted: February 3, 2015
Patent Number:
8949523
The present invention provides an HDD performance enhancement system that utilizes excess disk capacity as cache memory to enhance the I/O performance of the drive. The cache memory is distributed throughout the disk, for example in alternating tracks, sectors dedicated to serving as cache, or other distributed cache track segments or segment groups. Distributing the cache throughout the disk reduces the physical distance of the I/O head to the closest available cache location. The…
Self-journaling and hierarchical consistency for non-volatile storage
Granted: February 3, 2015
Patent Number:
8949517
A non-volatile storage system having Non-Volatile Memory (NVM) provides self-journaling and hierarchical consistency, enabling low-latency recovery and force unit access handshake. Mappings between host addresses and addresses in the NVM are maintained via one or more map entries, enabling locating of host data written to the NVM. Objects stored in the NVM include sufficient information to recover the object solely within the object itself. The NVM is managed as one or more data streams,…
Non-blocking processor bus bridge for network processors or the like
Granted: February 3, 2015
Patent Number:
8949500
Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a request from a first bus, the request having an identification field having a value. The request is then entered into one of a plurality of buffers having requests therein with the same identification field values. Which buffer receives the request may be based on a variety of techniques, such as random, least recently used, most full, prioritized, or sequential.…
Power gated memory device with power state indication
Granted: February 3, 2015
Patent Number:
8947966
A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.
Cross-talk compensation in array based reader systems
Granted: February 3, 2015
Patent Number:
8947806
A method of enhancing read performance in array-reader hardware includes generating, by the array-reader hardware, a plurality of signals, according to data read from a magnetic disk, and canceling at least a portion of cross-talk in the plurality of signals to generate a plurality of corrected signals.
Systems and methods for combined binary and non-binary data processing
Granted: February 3, 2015
Patent Number:
8947804
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.
