Self-journaling and hierarchical consistency for non-volatile storage
Granted: February 3, 2015
Patent Number:
8949517
A non-volatile storage system having Non-Volatile Memory (NVM) provides self-journaling and hierarchical consistency, enabling low-latency recovery and force unit access handshake. Mappings between host addresses and addresses in the NVM are maintained via one or more map entries, enabling locating of host data written to the NVM. Objects stored in the NVM include sufficient information to recover the object solely within the object itself. The NVM is managed as one or more data streams,…
Non-blocking processor bus bridge for network processors or the like
Granted: February 3, 2015
Patent Number:
8949500
Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a request from a first bus, the request having an identification field having a value. The request is then entered into one of a plurality of buffers having requests therein with the same identification field values. Which buffer receives the request may be based on a variety of techniques, such as random, least recently used, most full, prioritized, or sequential.…
Power gated memory device with power state indication
Granted: February 3, 2015
Patent Number:
8947966
A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.
Cross-talk compensation in array based reader systems
Granted: February 3, 2015
Patent Number:
8947806
A method of enhancing read performance in array-reader hardware includes generating, by the array-reader hardware, a plurality of signals, according to data read from a magnetic disk, and canceling at least a portion of cross-talk in the plurality of signals to generate a plurality of corrected signals.
Systems and methods for combined binary and non-binary data processing
Granted: February 3, 2015
Patent Number:
8947804
Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.
Thermal improvement of integrated circuit packages
Granted: February 3, 2015
Patent Number:
8946871
An integrated circuit package comprising an active semiconductor device layer and at least one heat-transfer semiconductor layer on the active semiconductor device layer. The heat-transfer semiconductor layer has a coefficient of thermal expansion that substantially matches a coefficient of thermal expansion of the active semiconductor device layer.
Multi-protocol storage controller
Granted: January 27, 2015
Patent Number:
8943234
Systems and methods presented herein provide for coupling a storage controller to a plurality of different storage device types. One embodiment of the storage controller includes an interface operable to communicatively couple to a storage device. The storage controller also includes a processor operable to select between hardware protocol detection of the storage device and firmware protocol detection of the storage device, and to detect a protocol of the storage device when the storage…
Common hot spare for multiple RAID groups
Granted: January 27, 2015
Patent Number:
8943359
A storage system assigns one or more large disks in a storage enclosure as a common dedicated hot spare that is used by multiple RAID groups. Storage space equivalent to the smallest physical disk in a RAID group is allocated on the common dedicated hot spare. A mapping of this allocated storage space to the RAID group is maintained in nonvolatile memory. When a disk fails in the RAID group, the allocated storage space on the common dedicated hot spare receives a rebuild of the failed…
Server direct attached storage shared through virtual SAS expanders
Granted: January 27, 2015
Patent Number:
8943258
A data storage system includes a first server including: a first plurality of storage disks configured to store data, and a first host bus adapter including a first processor configured to provide a first virtual expander and a first logic component; and a second server including: a second plurality of storage disks configured to store data, and a second host bus adapter including a second processor configured to provide a second virtual expander and a second logic component, wherein the…
Methods and structure for accounting for connection resets between peripheral component interconnect express bridges and host devices
Granted: January 27, 2015
Patent Number:
8943255
Methods and structure for accounting are provided for enhancing communications via a PCIE bridge. The bridge comprises a host interface that manages communications with a host device, and a PCIE interface that provides Memory Read Requests (MRds) to a PCIE device and receives Memory Read Completions (MRCs) from the PCIE device. The bridge also comprises a control unit that inserts tag information into the MRds. The control unit detects a reset of the host interface and revises the tag…
Interface for heterogeneous PCI-e storage devices
Granted: January 27, 2015
Patent Number:
8943226
Disclosed is a storage device interface. The storage device interface includes a plurality of PCIe device request engines. These PCIe device request engines receive I/O commands formatted for a respective one of a plurality of PCIe storage device communication standards. The storage device interface also includes a plurality of PCIe device completion engines. These PCIe device completion engines receive notifications of command completions from a plurality of PCIe storage devices that…
Threshold acquisition and adaption in NAND flash memory
Granted: January 27, 2015
Patent Number:
8942037
A method, apparatus, and controller for acquiring and tracking at least one threshold voltage of at least one cell of at least one flash chip. The method can include acquiring the at least one threshold voltage of a particular cell of the at least one flash cell. The method can further include performing at least one threshold voltage adjustment iteration.
Constant false alarm resonance detector
Granted: January 20, 2015
Patent Number:
8937781
A contact detection system includes a comparator operable to compare a signal derived from a contact sensor with a threshold and to indicate contact when the signal is greater than the threshold, a parameter estimation circuit operable to estimate parameters of a probability density function based on the signal derived from the contact sensor, and a threshold calculator operable to calculate the threshold based at least in part on the parameters of the probability density function.
Encryption key destruction for secure data erasure
Granted: January 20, 2015
Patent Number:
8938624
Techniques for encryption key destruction for secure data erasure via an external interface or physical key removal are described. Electrical destruction of key material retained in a memory of a storage device renders the device securely erased, even when the device is otherwise inoperable. The memory (e.g. non-volatile, such as flash) stores key material for encrypting/decrypting storage data for the device. An eraser provides power and commands to the memory, even when all or any…
Methods and systems using solid-state drives as storage controller cache memory
Granted: January 20, 2015
Patent Number:
8938574
Methods and systems for using one or more solid-state drives (SSDs) as a shared cache memory for a plurality of storage controllers coupled with the SSDs and coupled with a plurality of storage devices through a common switched fabric communication medium. All controllers share access to the SSDs through the switched fabric and thus can assume control for a failed controller by, in part, accessing cached data of the failed controller in the shared SSDs.
LDPC erasure decoding for flash memories
Granted: January 13, 2015
Patent Number:
8935595
A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash…
Concurrent, coherent cache access for multiple threads in a multi-core, multi-thread network processor
Granted: January 13, 2015
Patent Number:
8935483
Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A state engine operates on instructions received from the multi-thread instruction…
Offset-tolerant low noise amplifier
Granted: January 6, 2015
Patent Number:
8929012
The disclosure is directed to a low noise amplifier (LNA) configuration that compensates for DC offsets of incoming signals from a magnetoresistive head. According to various embodiments, the LNA includes a shunt-feedback differential pair of amplifiers adaptively biased according to a detected input DC voltage offset of the incoming signals from the magnetoresistive head. The LNA is thus enabled to amplify the AC signal component substantially unaffected by the DC offset. The DC…
Sync mark system for two dimensional magnetic recording
Granted: January 6, 2015
Patent Number:
8929011
A data processing system includes an analog to digital converter operable to sample an analog signal obtained from a magnetic storage medium to yield digital samples, and a sync mark detector operable to search for a particular one of a number of sync marks in the digital samples. Each of the data tracks on the magnetic storage medium is associated with one of the sync marks. The sync mark on each of the data tracks has a different pattern than the sync marks on neighboring tracks.
Systems and methods for loop pulse estimation
Granted: January 6, 2015
Patent Number:
8929010
A data processing system includes a digital data input operable to receive digital data, a digital data values input operable to receive values of the digital data, a loop pulse response estimation circuit operable to calculate a loop pulse response based on the digital data and the values of the digital data and based at least in part on past values of the loop pulse response, and a scaling circuit operable to scale the loop pulse response based at least in part on an absolute sum of…
