CIRCUIT AND METHOD FOR OPTIMIZING DYNAMIC RANGE IN A DIGITAL TO ANALOG SIGNAL PATH
Granted: July 26, 2012
Application Number:
20120188111
A circuit for maximizing dynamic range in a digital to analog signal path comprises an input for receiving an input signal, a first gain stage coupled to the input having a first gain setting, an second gain stage coupled to the first gain stage, the second gain stage having an second gain setting, a controller configured to selectively increase the first gain setting and decrease the second gain setting according to the input signal level and an output coupled to the second gain stage…
Negative Peak Voltage Detection for Enhanced FuelGauge Empty Voltage Prediction
Granted: June 21, 2012
Application Number:
20120153960
Negative peak voltage detection for battery end of life estimations in fuel gauging is disclosed. Battery powered devices such cell phones and laptop computers create some noise in the form of negative excursions from the average output voltage of the battery which can cause the battery powered device to stop functioning. By negative peak detection relative to the average battery voltage, the end of life or discharged voltage condition can be altered in response to the negative peaks to…
State Based Full and Empty Control for Rechargeable Batteries
Granted: June 7, 2012
Application Number:
20120139546
State based full and empty control for rechargeable batteries that will assure a uniform battery empty condition, even in the presence of a load on the battery. A fuel gauge provides a prediction of the open circuit voltage of the battery, and when the predicted open circuit voltage of the battery reaches the predetermined open circuit voltage of an empty battery, the load is terminated, after which the battery will relax back to the predetermined open circuit voltage of an empty…
USING MULTI-LEVEL PULSE WIDTH MODULATED SIGNAL FOR REAL TIME NOISE CANCELLATION
Granted: May 10, 2012
Application Number:
20120114033
A mixed signal processing circuit includes an analog to PWM converting circuit and a finite impulse response (FIR) filter having a multiple output tapped delay line and a summing and integration circuit. The mixed signal processing circuit converts an input analog signal to a PWM signal, forms a multi-level PWM signal from the PWM signal and one or more delayed versions of the PWM signal, and converts the multi-level PWM signal to an output analog signal. The analog to PWM converting…
Dual Laser-Power-Level Control and Calibration System for Burst-Mode and Continuous-Mode Transmitter
Granted: May 3, 2012
Application Number:
20120106953
Dual laser-power-level control and calibration system for burst-mode and continuous-mode transmitter. A first signal path receives a transmit signal that also drives the transmit laser, and a second signal path receives the output of a monitor diode. The first and second signal paths include filtering so that the two signal paths have a similar frequency response. The upper and lower excursions in both signal paths are compared, and the power levels of the optical transmitter are…
Integrated MOSFET Current Sensing for Fuel-Gauging
Granted: April 5, 2012
Application Number:
20120081125
Integrated MOSFET current sensing for fuel-gauging. A 1st MOSFET through which the current is to be sensed is coupled to a 2nd MOSFET of the same type, the 2nd MOSFET being biased to have the same resistance as the 1st MOSFET. The 2nd MOSFET has a much smaller area than the 1st MOSFET, and is coupled to a current source representing a maximum current through the 1st MOSFET. The voltage across the 1st MOSFET relative to the voltage across the 2nd MOSFET provides a measure of the current…
SYSTEMS AND METHODS FOR CONTROLLING INDUCTIVE ENERGY IN DC-DC CONVERTERS
Granted: April 5, 2012
Application Number:
20120081095
A DC-DC converter comprises a high-side switch, a low-side switch connected to the high-side switch, and an output capacitance. An inductance has one end connected to the high-side switch and the low-side switch and another end connected to the output capacitance. A shunting device circulates current flowing through the inductance back to the inductance during a load reduction transition to control a voltage across the output capacitance.
LOAD-SIDE VOLTAGE DETECTION VIA ELECTRIC METERING PROCESSING
Granted: March 29, 2012
Application Number:
20120078546
Load-side voltage detection via electric metering processing is disclosed. In one aspect, load-side voltage is provided as an input to a metering processing unit. The metering processing unit determines a voltage level of the load-side voltage. An application processing unit uses the voltage level to control operation of a service disconnect relay.
Systems And Methods For Digital Control Utilizing Oversampling
Granted: February 16, 2012
Application Number:
20120039376
Methods and systems for digital control utilizing oversampling.
SIDE WETTABLE PLATING FOR SEMICONDUCTOR CHIP PACKAGE
Granted: February 9, 2012
Application Number:
20120032352
A method for providing a semiconductor chip package with side wettable plating includes singulating a semiconductor chip package from an array of packages formed in a block format, immersing the semiconductor chip package in a bath of plating solution, contacting a lead land of the semiconductor chip package with conductive contact material within the bath of plating solution, connecting the conductive contact material to a cathode electrical potential, connecting an anode within the…
MULTI-SENSOR INTEGRATED CIRCUIT DEVICE
Granted: January 26, 2012
Application Number:
20120018827
A multiple sensor-types integrated circuit device includes a semiconductor die including a first sensor type and a second sensor type formed thereon, an electrically insulating package enclosing the semiconductor die and a plurality of electrically conductive leads coupled to the semiconductor die and extending from the package. By way of example and not limitation, a multiple sensor-types integrated circuit die includes a semiconductor substrate of a first polarity, a plurality of…
KEYPAD HAVING TAMPER-RESISTANT KEYS
Granted: January 26, 2012
Application Number:
20120018288
A tamper resistant keypad includes one or more key assemblies having a resilient key member and a contact. The resilient key member is configured to flex when the key assembly is depressed to allow the contact to close a key press detection circuit on a circuit board to register a key press. A tamper detection switch assembly at least partially surrounds the resilient key member. The tamper detection switch assembly is configured to detect attempts to access the key assembly.
SELF-CORRECTING ELECTRONIC SENSOR
Granted: December 29, 2011
Application Number:
20110320157
A temperature sensing circuit is described providing a low power temperature sensing system. The temperature sensing circuit provides a digital method for determining the temperature by analyzing the change in electrical response characteristics of a circuit device.
WAFER LEVEL PACKAGE (WLP) DEVICE HAVING BUMP ASSEMBLIES INCLUDING A BARRIER METAL
Granted: December 29, 2011
Application Number:
20110317385
WLP semiconductor devices include bump assemblies that have a barrier layer for inhibiting electromigration within the bump assemblies. In an implementation, the bump assemblies include copper posts formed on the integrated circuit chips of the WLP devices. Barrier layers formed of a metal such as nickel (Ni) are provided on the outer surface of the copper posts to inhibit electromigration in the bump assembly. Oxidation prevention caps formed of a metal such as tin (Sn) are provided…
USE OF DEVICE ASSEMBLY FOR A GENERALIZATION OF THREE-DIMENSIONAL METAL INTERCONNECT TECHNOLOGIES
Granted: December 8, 2011
Application Number:
20110300668
An assembly process properly positions and align a plurality of first die within a carrier substrate. The first die are positioned within cavities formed in the carrier substrate. The carrier substrate is then aligned with a second substrate having a plurality of second die fabricated therein. The first die and the second die are fabricated using different technologies. Aligning the carrier substrate and the second substrate aligns the first die with the second die. One or more first die…
HIGH SPEED DIGITAL TO ANALOG CONVERTER WITH REDUCED SPURIOUS OUTPUTS
Granted: December 8, 2011
Application Number:
20110299688
A system includes a first circuit including a scrambling module that receives N digital data streams and that scrambles the N digital data streams using a scrambling sequence. A data bus receives the N scrambled digital data streams and the scrambling sequence. A second circuit communicates with the data bus and includes a first processing module that processes the N scrambled digital data streams and that outputs M digital data streams, where M and N are integers greater than one. The…
HIGH SPEED DIGITAL-TO-ANALOG CONVERTER WITH LOW VOLTAGE DEVICE PROTECTION
Granted: December 8, 2011
Application Number:
20110299207
A digital-to-analog converter (DAC) includes a first DAC core, a second DAC core, and a butterfly switch. The first DAC core generates a first output. The second DAC core generates a second output. The butterfly switch includes at least one of switch transistors and cascode transistors. The butterfly switch selectively connects the first output and the second output to an output stage of the DAC.
Shared Operational Transconductance Amplifier Pipelined ADC Incorporating a Sample/Hold Amplifier and Multiple MDAC Stages
Granted: December 8, 2011
Application Number:
20110298645
A single operational transconductance pipelined ADC incorporating a sample/hold amplifier and multiple MDAC stages. An input signal is sampled on input signal sampling capacitors, and then coupled around an operational transconductance amplifier (OTA) so that the output of the OTA is equal to the sampled voltage. There is no net charge transfer in this operation, so the noise and power dissipation normally associated with an input sample and hold circuitry (SHA) in a pipelined ADC is…
DATA INTERFACE WITH DELAY LOCKED LOOP FOR HIGH SPEED DIGITAL TO ANALOG CONVERTERS AND ANALOG TO DIGITAL CONVERTERS
Granted: December 8, 2011
Application Number:
20110298508
A system comprises a first circuit includes a data transmitter circuit that transmits digital data based on a first clock signal. A sync generator outputs a sync signal based on the first clock signal. A digital to analog converter circuit includes a data receiver circuit that latches the digital data based on a second clock signal. A digital to analog converter core receives an output of the data receiver circuit. A delay locked loop circuit determines a delay based on the second clock…
SYNCHRONIZATION OF A GENERATED CLOCK
Granted: November 17, 2011
Application Number:
20110280109
A real time clock circuit is provided that has an onboard oscillator continuously providing an internal clock frequency, which is digitally synchronized to a more accurate reference clock frequency. An exemplary real time clock inhibits synchronization of the internal clock frequency when the reference clock is unavailable or if the reference clock's frequency is outside of a defined accuracy range.
