METHOD AND APPARATUS FOR IMPROVING DYNAMIC RANGE OF A TOUCHSCREEN CONTROLLER
Granted: October 27, 2011
Application Number:
20110261005
A touchscreen system for increasing the dynamic range of the system comprising a touchscreen coupled to an offset cancellation element and a capacitance measuring element. The offset cancellation element is configured to be dynamically changed in capacitance such that it offsets parasitic and sensor capacitances of the touchscreen sensors thereby leaving only touch event capacitance to be measured by the measuring element. The offset cancellation element is able to adjust to the initial…
SYSTEM FOR AND METHOD OF TRANSFERRING CHARGE TO CONVERT CAPACITANCE TO VOLTAGE FOR TOUCHSCREEN CONTROLLERS
Granted: October 27, 2011
Application Number:
20110261006
A touchscreen controller system determines the actual locations of multiple simultaneous touches by eliminating mutual capacitance between adjacent rows and columns during self-capacitance measurements and selectively enabling mutual capacitance during mutual capacitance measurements. During the self-capacitance measurements, the controller system generates a set of candidate touch locations, which includes the locations of real and ghost touches. During the mutual capacitance…
NOISE CANCELLATION TECHNIQUE FOR CAPACITIVE TOUCHSCREEN CONTROLLER USING DIFFERENTIAL SENSING
Granted: October 27, 2011
Application Number:
20110261007
A differential sensing scheme provides a means for detecting one or more touch events on a touch sensitive device in the presence of incident noise. Instead of sensing one touch sensitive channel, such as a row, column, or single touch sensor, multiple touch sensitive channels are sampled at a time. By sampling two nearby channels simultaneously and doing the measurement differentially, noise common to both channels is cancelled. The differential sensing scheme is implemented using…
USE OF RANDOM SAMPLING TECHNIQUE TO REDUCE FINGER-COUPLED NOISE
Granted: October 27, 2011
Application Number:
20110261008
Random sampling techniques include techniques for reducing or eliminating errors in the output of capacitive sensor arrays such as touch panels. The channels of the touch panel are periodically sampled to determine the presence of one or more touch events. Each channel is individually sampled in a round robin fashion, referred to as a sampling cycle. During each sampling cycle, all channels are sampled once. Multiple sampling cycles are performed such that each channel is sampled…
SYSTEM INTEGRATION OF TACTILE FEEDBACK AND TOUCHSCREEN CONTROLLER FOR NEAR-ZERO LATENCY HAPTICS PLAYOUT
Granted: October 27, 2011
Application Number:
20110260990
A haptic feedback system includes a user interface device, such as a touchscreen that includes a touch panel and one or more haptic drive elements coupled to the touch panel, a touch controller, and an actuator controller. The touch controller receives sensed data from the touch panel, and in response generates and sends a haptic signal to an actuator controller. Generation and transmission of the haptic signal bypasses any system host controller. A dedicated signal path couples the…
WAFER-LEVEL CHIP-SCALE PACKAGE DEVICE HAVING BUMP ASSEMBLIES CONFIGURED TO MITIGATE FAILURES DUE TO STRESS
Granted: October 13, 2011
Application Number:
20110248398
Wafer-level chip-scale package semiconductor devices are described that have bump assemblies configured to mitigate solder bump failures due to stresses, particularly stresses caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having two or more arrays of bump assemblies for mounting the device to a printed circuit…
CIRCUIT TOPOLOGY FOR PULSED POWER ENERGY HARVESTING
Granted: October 6, 2011
Application Number:
20110241625
An energy harvesting circuit harvests energy from a voltage source and charges a storage element with the harvested energy. The energy harvesting circuit includes an energy source, a storage capacitor to store energy output from the energy source, a power converter circuit, an energy storage element, and an enabling circuit. The enabling circuit turns the boost converter circuit on and off according to a monitored capacitance voltage of the storage capacitor. When the boost converter…
Low Noise Bandgap References
Granted: October 6, 2011
Application Number:
20110241646
Low noise bandgap voltage references using a cascaded sum of bipolar transistor cross coupled loops. These loops are designed to provide the total PTAT voltage necessary for one and two bandgap voltage references. The PTAT voltage noise is the square root of the sum of the squares of the noise voltage of each transistor in the loops. The total noise of the reference can be much lower than approaches using two or 4 bipolar devices to get a PTAT voltage and then gaining this PTAT voltage…
WAFER LEVEL PACKAGING WITH HEAT DISSIPATION
Granted: September 29, 2011
Application Number:
20110233756
A heat dissipating wafer level package and method for manufacturing a heat dissipating wafer level package is provided. The heat dissipating wafer level package has a thermally conductive coating integrated thereon which facilitates the dissipation of heat from a device into the surrounding air and/or the thermal transfer of heat away from the device toward a heat spreader or heat sink. Additionally, the coating enhances the structural integrity and strength of the wafer during the…
ENHANCED WLP FOR SUPERIOR TEMP CYCLING, DROP TEST AND HIGH CURRENT APPLICATIONS
Granted: September 22, 2011
Application Number:
20110227219
A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection.
Vertical Mosfet with Through-Body Via for Gate
Granted: September 22, 2011
Application Number:
20110227153
In an embodiment, set forth by way of example and not limitation, a MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The…
SWITCHED CAPACITOR AMPLIFIER CIRCUIT WITH CLAMPING
Granted: September 15, 2011
Application Number:
20110221520
A system comprises a switched capacitor amplifier including an operational amplifier (opamp). A switching circuit comprises a first switch connected across inputs of the opamp. A second switch is connected across outputs of the opamp. An overdrive detect circuit communicates with the first and second switches and selectively shorts the inputs and the outputs of the opamp when the input voltage is greater than a first predetermined overdrive voltage or when the input voltage is less than…
CIRCUIT TOPOLOGY FOR REGULATING POWER FROM LOW CAPACITY BATTERY CELLS
Granted: August 25, 2011
Application Number:
20110204855
A power circuit includes a voltage limited charge circuit and a linear regulator to supply high current pulses to a load while maintaining a regulated output and not discharging the battery below a predetermined level. The voltage limited charge circuit includes a low impedance transistor and an operational amplifier that are together configured as an active loop. The transistor functions as a switch, and the operational amplifier provides an adjustable control voltage that adjusts the…
WAFER-LEVEL PACKAGED DEVICE HAVING SELF-ASSEMBLED RESILIENT LEADS
Granted: August 18, 2011
Application Number:
20110198745
A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient…
ISOLATION MONITORING SYSTEM AND METHOD UTILIZING A VARIABLE EMULATED INDUCTANCE
Granted: July 28, 2011
Application Number:
20110181306
A system for measuring leakage resistance between a high voltage (HV) system of a vehicle and a vehicle chassis includes an emulated inductance that is connected between the HV system and the vehicle chassis and that has an inductive reactance that substantially cancels a capacitive reactance between the HV system and the vehicle chassis. A signal source outputs one of an AC current signal and an AC voltage signal between the HV system and the vehicle chassis. A sensor measures one of an…
ELECTROSTATIC MEMS DRIVER WITH ON-CHIP CAPACITANCE MEASUREMENT FOR AUTOFOCUS APPLICATIONS
Granted: July 14, 2011
Application Number:
20110169509
A driver and capacitance measuring circuit includes a voltage source that selectively generates an output voltage at a first node during a driver mode to alter a capacitance of a device that is connected to the first node and that has a variable capacitance. A current source selectively provides one of a charging and discharging current at the first node during a measurement mode. A capacitance calculating circuit samples a voltage at the first node during the measurement node,…
LOW DISTORTION MOS ATTENUATOR
Granted: June 30, 2011
Application Number:
20110156809
An attenuation circuit uses a voltage controlled variable resistance transistor as a signal attenuator for receivers operating in the zero Hz to about 30 MHz range. The transistor functions in the linear region to linearize the transistor resistance characteristics used for signal attenuation. In an exemplary application, the attenuation circuit is used as an RF attenuator for AM radio broadcast receivers and amplifiers with automatic gain control. Multiple attenuation circuits can be…
ACTIVE PARASITE POWER CIRCUIT
Granted: June 23, 2011
Application Number:
20110149623
A circuit is provided that includes a parasitic power circuit that powers a parasitic circuit. The parasitic power circuit derives a supply voltage from an external AC or other signal suitable for use as a communications signal. A PMOS transistor or transistors is utilized to enable a supply voltage capacitor to charge substantially to the same voltage as the channel voltage of the communications signal.
MOS POWER TRANSISTOR
Granted: May 19, 2011
Application Number:
20110115018
A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region of the substrate, and a second portion forming a polysilicon field plate formed over a portion of a transition…
CMOS COMPATIBLE LOW GATE CHARGE LATERAL MOSFET
Granted: May 19, 2011
Application Number:
20110115019
A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a switching gate positioned over a first portion of a channel region of the substrate, and a second portion forming a static gate formed over a second portion of the…
