MIPI TRANSLATION IN GIGABIT MULTIMEDIA SERIAL LINK
Granted: June 29, 2023
Application Number:
20230208946
Systems and methods provide secure, end-to-end high-speed data encoding and communication. In certain embodiments, this is accomplished by modifying a header portion of a data packet received from a first device and complying with a one Mobile Industry Processor Interface (MIPI) protocol to create a modified data packet that complies with a faster MIPI protocol. The header portion of the modified data packet is validated during a tunnel mode operation using an error detection process to…
BROADBAND ON-CHIP NESTED-LOOP ALTERNATING CURRENT (AC)-COUPLING SYSTEMS AND METHODS
Granted: June 1, 2023
Application Number:
20230170852
Various embodiments of the invention provide for an AC-coupling method and systems that utilize a nested loop circuit to generate a differential mode output that facilitates an offset compensation and a common mode output that facilitates DC-biasing of an active circuit. In embodiments, the nested loop circuit comprises a differential amplifier and a differential mode loop that generates a differential mode output and a common mode loop that uses a common mode voltage and a reference…
SYSTEMS AND METHODS FOR ASYMMETRIC IMAGE SPLITTER CLOCK GENERATION
Granted: May 18, 2023
Application Number:
20230156149
Described herein are systems and methods that provide for asymmetric image splitter image stream applications. In one embodiment, a system supporting image multi-streaming comprises an asymmetric image splitter engine that splits super-frame image streams into two or more image streams and a fractional clock divider circuit. The fractional clock divider may comprise a digital feedback control loop and a one-bit sigma delta modulator. The fractional clock divider circuit may provide…
SYSTEMS AND METHODS FOR INCREASING HARDWARE ACCELERATOR PERFORMANCE IN NEURAL NETWORK APPLICATIONS
Granted: April 6, 2023
Application Number:
20230108883
Low-power systems and methods increase computational efficiency in neural network processing by allowing hardware accelerators to perform processing steps on large amounts of data at reduced execution times without significantly increasing hardware cost. In various embodiments, this is accomplished by accessing locations in a source memory coupled to a hardware accelerator and using a resource optimizer that based on storage availability and network parameters determines target locations…
TRANSMITTING CLOCK REFERENCE OVER REVERSE CHANNEL IN A BIDIRECTIONAL SERIAL LINK
Granted: March 16, 2023
Application Number:
20230081578
A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector…
POWER MODULATION USING DYNAMIC VOLTAGE AND FREQUENCY SCALING
Granted: March 16, 2023
Application Number:
20230079229
Non-intrusive, low-cost systems and methods allow designers to reduce headroom and safety margin requirements in the context of compute circuits, such as machine learning circuits, without increasing footprint or having to sacrifice computing capacity and other valuable resources. Various embodiments accomplish this by taking advantage of certain properties of machine learning circuits and using a CNN as a diagnostic tool for evaluating circuit behavior and adjusting circuit parameters…
DYNAMIC DATA-DEPENDENT NEURAL NETWORK PROCESSING SYSTEMS AND METHODS
Granted: March 16, 2023
Application Number:
20230077454
Dynamic data-dependent neural network processing systems and methods increase computational efficiency in neural network processing by uniquely processing data based on the data itself and/or configuration parameters for processing the data. In embodiments, this is accomplished by receiving, at a controller, input data that is to be processed by a first device in a first layer of a sequence of processing layers of a neural network using a first set of parameters. The input data is…
NARROW PULSE WIDTHS IN H-BRIDGE BUCK-BOOST DRIVERS
Granted: February 9, 2023
Application Number:
20230041463
Described herein are systems and methods for generating short load current pulses using an H-bridge. In various embodiments, this is accomplished by controlling, in a shunting mode, a low-side switch of the H-bridge to drive a first average current and controlling, in a non-shunting mode, a high-side switch of the H-bridge to drive a second average current such that the first and second average currents are substantially the same and reduce a current pulse width of the load current.
NARROW PULSE WIDTHS IN H-BRIDGE BUCK-BOOST DRIVERS
Granted: February 9, 2023
Application Number:
20230041463
Described herein are systems and methods for generating short load current pulses using an H-bridge. In various embodiments, this is accomplished by controlling, in a shunting mode, a low-side switch of the H-bridge to drive a first average current and controlling, in a non-shunting mode, a high-side switch of the H-bridge to drive a second average current such that the first and second average currents are substantially the same and reduce a current pulse width of the load current.
METHOD AND CIRCUIT ASSEMBLY FOR THE RESONANCE DAMPING OF STEPPER MOTORS
Granted: December 29, 2022
Application Number:
20220416699
A method and a circuit arrangement for damping stepper motor resonances during operation of a stepper motor (M), in particular in the medium und high speed range, is described, wherein the coils (A; B) of the stepper motor (M) are each connected into a bridge circuit (Br 1; Br2) comprising semiconductor switches (Sw1, . . . Sw4), in order to impress into the coils (A; B) a predetermined target coil current (ISollA; ISollB). The resonance damping is essentially achieved by activating a…
SYSTEMS AND METHODS FOR REDUCING POWER CONSUMPTION IN COMPUTE CIRCUITS
Granted: December 29, 2022
Application Number:
20220413590
Systems and methods increase computational efficiency in machine learning accelerators. In embodiments, this is accomplished by evaluating, partitioning, and selecting computational resources to uniquely process, accumulate, and store data based on the type of the data and configuration parameters that are used to process the data. Various embodiments, take advantage of the zeroing feature of a Built-In Self-Test (BIST) controller to cause a BIST circuit to create a known state for a…
SYSTEMS AND METHODS FOR CONTROLLING POWERSTAGE SUPPLY MODULATION VIA AUDIO INTERFACE
Granted: December 22, 2022
Application Number:
20220408182
Systems and methods increase power efficiency in communication systems by examining a digital signal to determine whether a threshold corresponding to an increase in a power requirement is likely to be exceeded. The signal is encoded with information indicating the likely change and communicated to a driver that, upon extracting the information, uses it to cause instruct an amplifier to increase a power output to accommodate the increase in power requirement. Once the threshold is no…
POWER CONTROL SYSTEMS AND METHODS FOR MACHINE LEARNING COMPUTING RESOURCES
Granted: December 15, 2022
Application Number:
20220397954
Described are context-aware low-power systems and methods that reduce power consumption in compute circuits such as commonly available machine learning hardware accelerators that carry out a large number of arithmetic operations when performing convolution operations and related computations. Various embodiments exploit the fact that power demand for a series of computation steps and many other functions a hardware accelerator performs is highly deterministic, thus, allowing for energy…
HIGH-VOLTAGE, BIDIRECTIONAL PROTECTION CIRCUITS AND METHODS
Granted: December 8, 2022
Application Number:
20220393463
Systems and methods herein use a sensing circuit to detect an overvoltage at a voltage node as a drain current. A current-mode comparator converts the detected current into a control signal, which is provided to a control circuit. The control circuit uses the control signal cut of a bias current to turn off switches in a protection circuit to create a high-impedance electrical path between the voltage node and the to-be-protected voltage node.
SYSTEMS AND METHODS FOR FAULT DETECTION AND REPORTING THROUGH SERIAL INTERFACE TRANSCEIVERS
Granted: December 8, 2022
Application Number:
20220390507
Circuitry, systems, and methods for fault detection and reporting comprise a fault detection circuit configured to detect one or more fault conditions that cause a state change in a fault pin voltage representative of a transceiver failure. Once the state of the fault pin voltage changes, a transceiver input generates a fault detection code. In embodiments, in response to the transceiver input receiving a first signal, the fault detection code is shifted to a transceiver output that may…
Systems and Methods for Performing In-Flight Computations
Granted: December 1, 2022
Application Number:
20220382361
In-flight operations in an inbound data path from a source memory to a convolution hardware circuit increase computational throughput when performing convolution calculations, such as pooling and element-wise operations. Various operations may be performed in-line within an outbound data path to a target memory. Advantageously, this drastically reduces extraneous memory access and associated read-write operations, thereby, significantly reducing overall power consumption in a computing…
STORAGE-EFFICIENT SYSTEMS AND METHODS FOR DEEPLY EMBEDDED ON-DEVICE MACHINE LEARNING
Granted: November 17, 2022
Application Number:
20220366261
Storage-efficient, low-cost systems and methods provide embedded systems with the ability to dynamically perform on-device learning to modify or customize a trained model to improve computing and detection accuracy in small-scale devices. In certain embodiments, this is accomplished by repurposing storage elements from inference to training and performing partial back-propagation in embedded devices in the final layers of an existing network. In various embodiments replacing weights in…
SYSTEMS AND METHODS FOR REDUCING POWER CONSUMPTION IN COMPUTE CIRCUITS
Granted: November 17, 2022
Application Number:
20220366225
Systems and methods allow existing hardware, such as commonly available hardware accelerators to process fully connected network (FCN) layers in an energy-efficient manner and without having to implement additional expensive hardware. Various embodiments, accomplish this by using a “flattening” method that converts a channel associated with a number of pixels into a number of channels that equals the number pixels.
SYSTEMS AND METHODS FOR REDUCING POWER CONSUMPTION IN EMBEDDED MACHINE LEARNING ACCELERATORS
Granted: October 20, 2022
Application Number:
20220334634
Systems and methods reduce power consumption in embedded machine learning hardware accelerators and enable cost-effective embedded at-the-edge machine-learning and related applications. In various embodiments this may be accomplished by using hardware accelerators that comprise a programmable pre-processing circuit that operates in the same clock domain as the accelerator. In some embodiments, tightly coupled data loading first-in-first-out registers (FIFOs) eliminate clock…
FAULT ATTACK RESISTANT CRYPTOGRAPHIC SYSTEMS AND METHODS
Granted: September 8, 2022
Application Number:
20220286270
Described herein are systems and methods that prevent against fault injection attacks. In various embodiments this is accomplished by taking advantage of the fact that an attacker cannot utilize a result that has been faulted to recover a secret. By using infective computation, an error is propagated in a loop such that the faulted value will provide to the attacker no useful information or information from which useful information may be extracted. Faults from a fault attack will be so…
